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Yvon SavariaDépartement de génie électrique
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Allard, F. J. X., Ould-Bachir, T., & Savaria, Y. (juin 2024). Enhancing P4 syntax to support extended finite state machines as native stateful objects [Communication écrite]. 2024 IEEE 10th International Conference on Network Softwarization (NetSoft), Saint Louis, MO, USA. Lien externe
Azodi, M., Sadrossadat, S. A., & Savaria, Y. (2024). Nonlinear circuit macromodeling using new heterogeneous-layered deep clockwork recurrent neural network. IEEE Access, 12, 89506-89519. Disponible
Ahmed, M., Genevey, S., Ali, M., Savaria, Y., & Audet, Y. (2024). Recent start-up techniques intended for TEG energy harvesting: a review. IEEE Access, 12, 34116-34130. Disponible
Amer, M., Abuelnasr, A., Ali, M., Hassan, A., Trigui, A., Ragab, A., Sawan, M., & Savaria, Y. (2024). Enhanced dynamic regulation in Buck Converters: integrating input-voltage feedforward with voltage-mode feedback. IEEE Access, 12, 7310-7328. Disponible
Alizadeh, R., Savaria, Y., & Nerguizian, C. (2024). Characterization and selection of WiFi channel state information features for human activity detection in a smart public transportation system. IEEE Open Journal of Intelligent Transportation Systems, 5, 55-69. Disponible
Ahmed, M., Trigui, A., Genevey, S., Audet, Y., & Savaria, Y. (2024). A 32-mV Supply Ring Oscillator Composed of Modified Schmitt Trigger Delay Cells for Integrated Start-up Circuits in DC Energy Harvesting Systems. IEEE Access, 3457839 (13 pages). Lien externe
Abuelnasr, A., Ragab, A., Amer, M., Gosselin, B., & Savaria, Y. (2024). Incremental reinforcement learning for multi-objective analog circuit design acceleration. Engineering Applications of Artificial Intelligence, 129, 107426 (18 pages). Lien externe
Abbasmollaei, M., Ould-Bachir, T., & Savaria, Y. (mai 2024). Normal and Resilient Mode FPGA-based Access Gateway Function Through P4-generated RTL [Communication écrite]. 2024 20th International Conference on the Design of Reliable Communication Networks (DRCN 2024), Montreal, Qc, Canada. Lien externe
Abuelnasr, A., Amer, M., Ali, M., Hassan, A., Gosselin, B., Ragab, A. R. A., & Savaria, Y. (2023). Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(4), 1555-1565. Disponible
Askarihemmat, M., Wagner, S., Bilaniuk, O., Hariri, Y., Savaria, Y., & David, J. P. (janvier 2023). BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU [Communication écrite]. 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023), Tokyo, Japan. Lien externe
Alizadeh, R., Savaria, Y., & Nerguizian, C. (décembre 2023). Enabling Human Activity Recognition in Smart Public Transportation Systems in Presence of Dataset Imbalance [Communication écrite]. 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2023), Istanbul, Turkey (5 pages). Lien externe
Amer, M., Abuelnasr, A., Hassan, A., Ragab, A., Sawan, M., & Savaria, Y. (2023). A Half-bridge Gate Driver with Self-adjusting and Tunable Dead-time Modes for Efficient Switched-mode Power Systems. IEEE Transactions on Power Electronics, 15 pages. Lien externe
Assaf, H., Savaria, Y., Ali, M., Nabavi, M., & Sawan, M. (2023). A Memristive Cell with Long Retention Time in 65 nm CMOS Technology. Advanced Electronic Materials, 9(6), 13 pages. Lien externe
AskariHemmat, M.H., Dupuis, T., Fournier, Y., El Zarif, N., Cavalcante, M., Perotti, M., Gurkaynak, F., Benini, L., Leduc-Primeau, F., Savaria, Y., & David, J. P. Quark: an integer RISC-V vector processor for sub-byte quantized DNN inference [Communication écrite]. 2023 IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, CA, USA (5 pages). Lien externe
Alizadeh, R., Savaria, Y., & Nerguizian, C. (octobre 2022). Automatic Detection of People Getting Into a Bus in a SMART Public Transportation System [Communication écrite]. 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2022), Glasgow, Scotland. Lien externe
Abadi, A. F. E., Asghari, S. A., Marvasti, M. B., Abaei, G., Nabavi, M., & Savaria, Y. (2022). RLBEEP: Reinforcement-Learning-Based Energy Efficient Control and Routing Protocol for Wireless Sensor Networks. IEEE Access, 10, 44123-44135. Lien externe
Ali, M., Hassan, A., Honarparvar, M., Nabavi, M., Audet, Y., Sawan, M., & Savaria, Y. (2022). A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges. IEEE Access, 10, 24540-24555. Lien externe
Ali, M., Elsayed, A., Mendez, A., Savaria, Y., & Sawan, M. (2021). Contact and remote breathing rate monitoring techniques: a review. IEEE Sensors Journal, 21(13), 14569-14586. Disponible
Abuelnasr, A., Amer, M., Ragab, A., Gosselin, B., & Savaria, Y. (mai 2021). Causal information prediction for analog circuit design using variable selection methods based on machine learning [Communication écrite]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). Lien externe
Alhousseiny, I., Ali, M., Ben-Hamida, N., Honarparvar, M., Sawan, M., & Savaria, Y. (novembre 2021). Delay-Locked Loop Based Multiphase Clock Generator for Time-Interleaved ADCs [Communication écrite]. 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2021), Dubai, United Arab Emirates (4 pages). Lien externe
Amer, M., Abuelnasr, A., Ragab, A., Hassan, A., Ali, M., Gosselin, B., Sawan, M., & Savaria, Y. (mai 2021). Design and analysis of combined input-voltage feedforward and PI controllers for the buck converter [Communication écrite]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). Lien externe
Alizadeh, R., Savaria, Y., & Nerguizian, C. (octobre 2021). Human Activity Recognition and People Count for a SMART Public Transportation System [Communication écrite]. 4th IEEE 5G World Forum (5GWF 2021), Montreal, Québec. Lien externe
Akbari, M., Honarparvar, M., Savaria, Y., & Sawan, M. (2021). Power Bound Analysis of a Two-Step MASH Incremental ADC Based on Noise-Shaping SAR ADCs. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(8), 3133-3146. Lien externe
AskariHemmat, M.H., Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (mai 2021). RISC-V barrel processor for deep neural network acceleration [Communication écrite]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). Lien externe
Amer, M., Ali, M., Abuelnasr, A., Hassan, A., Nabavi, M., Savaria, Y., & Sawan, M. (juin 2020). Fully integrated dual-channel gate driver and area efficient pid compensator for surge tolerant power sensor interface [Communication écrite]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Qc, Canada. Lien externe
Akbari, M., Honarparvar, M., Savaria, Y., & Sawan, M. (octobre 2020). OTA-free MASH 2-2 noise shaping SAR ADC: System and design considerations [Communication écrite]. 52nd IEEE International Symposium on Circuits and Systems (ISCAS 2020) (5 pages). Lien externe
Akbari, M., Honarparvar, M., Savaria, Y., & Sawan, M. (juin 2020). OTA-free MASH Two-step Incremental ADC based on Noise Shaping SAR ADCs [Communication écrite]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Qc, Canada. Lien externe
Askarihemmat, M.H., Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (mai 2020). RISC-V Barrel Processor for Accelerator Control [Communication écrite]. 28th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2020), Fayetteville, AR (1 page). Lien externe
Abuelnasr, A., Ali, M., Amer, M., Nabavi, M., Hassan, A., Gosselin, B., & Savaria, Y. (octobre 2020). Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2020), Sevilla, Spain (5 pages). Lien externe
Ammar, M., Hamad, G. B., Mohamed, O. A.̈., & Savaria, Y. (2019). System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs). Dans Velazco, R., McMorrow, D., & Estela, J. (édit.), Radiation Effects on Integrated Circuits and Systems for Space Applications (p. 13-38). Lien externe
AskariHemmat Hossein, M., Savaria, Y., Jean-Pierre, D., Honari, S., Perone, C., Rouhier, L., & Cohen-Adad, J. (octobre 2019). Fixed-point u-net quantization for medical image segmentation [Communication écrite]. 22nd International Conference on Medical Image Computing & Computer Assisted Intervention (MICCAI 2019), Shenzhen, China. Non disponible
Assaf, H., Savaria, Y., & Sawan, M. (mars 2019). Memristor Emulators for an Adaptive DPE Algorithm: Comparative Study [Communication écrite]. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2019), Hsinchu, Taiwan. Lien externe
Ammar, M., Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (2019). Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-trees (TDFTs). IEEE Access, 7, 29264-29276. Lien externe
AskariHemmat, M.H., Honari, S., Rouhier, L., Perone, C. S., Cohen-Adad, J., Savaria, Y., & David, J. P. (octobre 2019). U-net fixed-point quantization for medical image segmentation [Communication écrite]. 1st International Workshop on Hardware Aware Learning for Medical Imaging and Computer Assisted Intervention (HAL-MICCAI 2019), Shenzhen, China. Lien externe
Ali, M., Nabavi, M., Hassan, A., Honarparvar, M., Savaria, Y., & Sawan, M. (décembre 2019). A versatile SoC/SiP sensor interface for industrial applications: Design considerations [Communication écrite]. 31st International Conference on Microelectronics (ICM 2019), Cairo, Egypt. Lien externe
Amer, M., Hassan, A., Ragab, A., Yacout, S., Savaria, Y., & Sawan, M. (mai 2018). High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy. Lien externe
Abubakr, A., Hassan, A., Ragab, A., Yacout, S., Savaria, Y., & Sawan, M. (mai 2018). High-temperature modeling of the I-V characteristics of GaN150 HEMT using machine learning techniques [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italie (5 pages). Lien externe
Ammar, M., Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (décembre 2018). Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMC [Communication écrite]. 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2018), Bordeaux, France. Lien externe
Assaf, H., Savaria, Y., & Sawan, M. (décembre 2018). Vector matrix multiplication using crossbar arrays: a comparative analysis [Communication écrite]. 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2018), Bordeaux, France. Lien externe
Ammar, M., Bany Hamad, G., Mohamed, O. A., Savaria, Y., & Velazco, R. (septembre 2016). Comprehensive vulnerability analysis of systems exposed to SEUs via probabilistic model checking [Communication écrite]. 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2016), Bremen, Germany (4 pages). Lien externe
Ammar, M., Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (2017). System-Level Analysis of the Vulnerability of Processors Exposed to Single Event Upsets via Probabilistic Model Checking. IEEE Transactions on Nuclear Science, 64(9), 2523-2530. Lien externe
Ammar, M., Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (septembre 2016). Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking [Communication écrite]. Forum on Specification and Design Languages (FDL 2016), Bremen, Germany (8 pages). Lien externe
Alizadeh, R., & Savaria, Y. (décembre 2016). Performance analysis of a reduced complexity SCMA decoder exploiting a low-complexity maximum-likelihood approximation [Communication écrite]. 23rd IEEE International Conference on Electronics Circuits and Systems (ICECS 2016), Monte Carlo, Monaco. Lien externe
Alizadeh, R., Belanger, N., Savaria, Y., & Boyer, F.-R. (juin 2016). Performance characterization of an SCMA decoder [Communication écrite]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Lien externe
Alizadeh, R., Bélanger, N., Savaria, Y., & Frigon, J.-F. (juin 2015). DPDK and MKL; enabling technologies for near deterministic cloud-based signal processing [Communication écrite]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Lien externe
Abdollahifakhr, H., Bélanger, N., Savaria, Y., & Gagnon, F. (juin 2015). Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum [Communication écrite]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Lien externe
Al-bayati, Z., Ait Mohamed, O., Rafay Hasan, S., & Savaria, Y. (décembre 2012). Design of a C-element based clock domain crossing interface [Communication écrite]. 24th International Conference on Microelectronics (ICM 2012), Algiers, Algeria (4 pages). Lien externe
Al-Bayati, Z., Ait Mohamed, O., Hasan, S. R., & Savaria, Y. (mai 2012). A novel hybrid FIFO asynchronous clock domain crossing interfacing method [Communication écrite]. 22nd Great Lakes Symposium on VLSI (GLSVLSI 2012), Salt Lake City, Utah. Lien externe
Al-Bayati, Z., Ait Mohamed, O., Savaria, Y., & Boukadoum, M. (juin 2012). Probabilistic model checking of clock domain crossing interfaces [Communication écrite]. 10th IEEE International New Circuits and Systems Conference (NEWCAS 2012), Montréal, Québec. Lien externe
Al-Terkawi Hasib, O., André, W., Blaquière, Y., & Savaria, Y. (mai 2012). Propagating analog signals through a fully digital network on an electronic system prototyping platform [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. Lien externe
Aubertin, P., Langlois, J. M. P., & Savaria, Y. (2012). Real-time computation of local neighborhood functions in application-specific instruction-set processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(11), 2031-2043. Lien externe
Anane, A., Aboulhamid, E. M., & Savaria, Y. (juillet 2012). System modeling and multicore simulation using transactions [Communication écrite]. International Conference on Embedded Computer Systems (SAMOS 2012), Samos, Grèce. Lien externe
Allard, M., Grogan, P., Savaria, Y., & David, J. P. (mai 2012). Two-level configuration for FPGA: A new design methodology based on a computing fabric [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. Lien externe
Al-Terkawi Hasib, O., Sawan, M., & Savaria, Y. (2011). A low-power asynchronous step-down DCDC converter for implantable devices. IEEE Transactions on Biomedical Circuits and Systems, 5(3), 292-301. Lien externe
Ayachi, D., Savaria, Y., & Thibeault, C. (juin 2009). A configurable platform for MPSoCs based on application specific instruction set processors [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France (4 pages). Lien externe
Aubertin, P., Mohammadi, H. M., Savaria, Y., & Langlois, J. M. P. (juin 2009). High performance ASIP implementation of PBDI: a new intra-field deinterlacing method [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Anane, A., Aboulhamid, E. M., Vachon, J., & Savaria, Y. (mai 2008). Modeling and simulation of complex heterogeneous systems [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, WA, United states. Lien externe
Abderrahman, A., Savaria, Y., Khouas, A., & Sawan, M. (août 2007). Accurate testability analysis based-on multi-frequency test generation and a new testability metric [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. Lien externe
Abderrahman, A., Savaria, Y., Khouas, A., & Sawan, M. (décembre 2007). New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches [Communication écrite]. 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco. Lien externe
Adham, S. M. I., Savaria, Y., Antaki, B., & Xiong, N. (2000). Voltage excursion detection apparatus. (Brevet no US6100716). Lien externe
Antaki, B., Savaria, Y., Saman, A., Xiong, N., Borrione, D., & Ernst, R. (mars 1999). Design for testability method for CML digital circuits [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 1999), Munich, Germany. Lien externe
Audet, D., Masson, S., & Savaria, Y. (novembre 1998). Reducing fault sensitivity of microprocessor-based systems by modifying workload structure [Communication écrite]. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 1998), Austin, TX. Lien externe
Antaki, B., Patenaude, S., Trognon, L., & Savaria, Y. (juin 1997). Study on split-output TSPC CMOS circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong. Lien externe
Abderrahman, A., Savaria, Y., & Kaminska, B. (1996). Analyse, estimation et réduction du bruit de commutation simultanée. [Analysis, estimation and reduction of simultaneous switching noise]. Canadian Journal of Electrical and Computer Engineering, 21(4), 133-143. Lien externe
Audet, D., Gagnon, N., & Savaria, Y. (janvier 1996). Implementing fault injection and tolerance mechanisms in multiprocessor systems [Communication écrite]. IEEE Workshop on Defect and Fault Tolerance in VLSI (DFT 1996), Boston. Lien externe
Audet, D., Gagnon, F., & Savaria, Y. (janvier 1996). Quantitative comparisons of TMR implementations in a multiprocessor system [Communication écrite]. 3rd IEEE On-Line Testing Workshop, Biarritz. Non disponible
Audet, D., & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the host interface. (Rapport technique). Non disponible
Audet, D., & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the routers, from a functional to a detailed implementation description. (Rapport technique). Non disponible
Audet, D., Savaria, Y., & Arel, N. (1995). Effective ultra large scale integration (ULSI) architecture techniques: FATMOS, a fault-tolerant multiprocessor operating system. (Rapport technique). Non disponible
Audet, D., & Savaria, Y. (1995). High-speed interconnections using true single-phase clocking. Journal of Microelectronic Systems Integration, 3(4), 247-257. Non disponible
Audet, D., & Savaria, Y. High-speed interconnections using true single-phase clocking [Communication écrite]. 7th IEEE Annual International Conference on Wafer Scale Integration, San Francisco, Ca, USA. Lien externe
Audet, D., & Savaria, Y. (1994). Architectural approach for increasing clock frequency and communication speed in monolithic WSI systems. IEEE Transactions on Components Packaging and Manufacturing Technology. Part B, Advanced Packaging, 17(3), 362-368. Lien externe
Audet, D., Savaria, Y., & Arel, N. (janvier 1994). Architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems [Communication écrite]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, California. Lien externe
Abderrahman, A., Kaminska, B., & Savaria, Y. (février 1994). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits [Communication écrite]. European Design and Test Conference, Paris, Fr. Lien externe
Audet, D., Savaria, Y., & Arel, N. (1994). Pipelining communications in large VLSI/ULSI systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1), 1-10. Lien externe
Audet, D., Savaria, Y., & Houle, J.-L. (1992). Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources. Parallel Computing, 18(2), 149-167. Lien externe
Audet, D., Chouinard, G., Cyr, C., Houle, J.-L., & Savaria, Y. (1988). IMAGE2 : un circuit multiprocesseur pour le traitement parallèle. (Rapport technique n° EPM-RT-88-35). Accès restreint
Audet, D., Savaria, Y., & Houle, J.-L. (1988). Performance improvements of VLSI parallel systems, using dynamic concatenation of processing resources. (Rapport technique n° EPM-RT-88-36). Accès restreint
Bensalem, H., Blaquière, Y., & Savaria, Y. (2023). An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(3), 1144-1148. Lien externe
Bensalem, H., Blaquiere, Y., & Savaria, Y. (mai 2021). Acceleration of the secure hash algorithm-256 (SHA-256) on an FPGA-CPU cluster using OpenCL [Communication écrite]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). Lien externe
Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (2021). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models. Dans The Lognormality Principle and its Applications in e-Security, e-Learning and e-Health (Vol. 88, p. 309-325). Lien externe
Berrima, S., Blaquiere, Y., & Savaria, Y. (2021). Ring-Oscillator Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Transactions on Instrumentation and Measurement, 70, 1-10. Lien externe
Berrima, S., Blaquiere, Y., & Savaria, Y. (2020). Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices & Systems, 14(8), 1243-1252. Lien externe
Bensalem, H., Blaquiere, Y., & Savaria, Y. (2020). In-FPGA instrumentation framework for openCL-based designs. IEEE Access, 8, 212979-212994. Disponible
Bensenouci, M. A., Ali, M., Escid, H., Savaria, Y., & Sawan, M. (décembre 2020). A VCO-Based Nonuniform Sampling ADC Using a Slope-Dependent Pulse Generator [Communication écrite]. 32nd International Conference on Microelectronics (ICM 2020), Aqaba, Jordan (4 pages). Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). HPQS: A fast, high-capacity, hybrid priority queuing system for high-speed networking devices. IEEE Access, 7, 130672-130684. Disponible
Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). A high-speed, scalable, and programmable traffic manager architecture for flow-based networking. IEEE Access, 7, 2231-2243. Disponible
Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (mai 2019). Bit-slicing FPGA accelerator for quantized neural networks [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). Lien externe
Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (juin 2019). Combining Interval Arithmetic with the Branch and Bound Algorithm for Delta-lognormal Parameter Extraction [Communication écrite]. International Conference of the International Graphonomics Society, Cancun, Mexico (5 pages). Non disponible
Benyoussef, M., Thibeault, C., & Savaria, Y. (mai 2019). A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). Lien externe
Bensalem, H., Blaquiere, Y., & Savaria, Y. (mai 2019). Toward in-system monitoring of OpenCL-based designs on FPGA [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (mai 2018). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). Lien externe
Berrima, S., Blaquière, Y., & Savaria, Y. (2018). Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integration, 62, 159-169. Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952. Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (juin 2018). HPQ: a high capacity hybrid priority queue architecture for high-speed network switches [Communication écrite]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. Lien externe
Bany Hamad, G., Ammar, M., Mohamed, O. A., & Savaria, Y. (2018). New insights into soft-faults induced cardiac pacemakers malfunctions analyzed at system-level via model checking. IEEE Access, 6, 62107-62119. Lien externe
Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (mai 2018). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models [Communication écrite]. International Conference on Pattern Recognition and Artificial Intelligence (ICPRAI 2018), Montréal, Québec. Non disponible
Bany Hamad, G., Ammar, M., Mohamed, O. A., & Savaria, Y. (septembre 2018). System-Level Characterization, Modeling, and Probabilistic Formal Analysis of LEON3 Vulnerability to Transient Faults [Communication écrite]. 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2018), Piscataway, NJ, USA (4 pages). Lien externe
Bany Hamad, G., Kazma, G., Mohamed, O. A., & Savaria, Y. (juillet 2017). Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT [Communication écrite]. 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece. Lien externe
Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (2017). Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits. Journal of Electronic Testing: Theory and Applications, 33(5), 607-620. Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (juin 2017). A high-speed traffic manager architecture for flow-based networking [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (septembre 2016). Investigating the efficiency of cell level hardening techniques of single event transients via SMT [Communication écrite]. 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2016), Bremen, Germany (4 pages). Lien externe
Berrima, S., Blaquière, Y., & Savaria, Y. (mai 2017). A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD (4 pages). Lien externe
Berrima, S., Blaquiere, Y., & Savaria, Y. (août 2017). Sub-ps resolution programmable delays implemented in a Xilinx FPGA [Communication écrite]. 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Boston, MA. Lien externe
Bany Hamad, G., Kazma, G., Mohamed, O. A., & Savaria, Y. (septembre 2016). Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients [Communication écrite]. Forum on Specification and Design Languages (FDL 2016), Bremen, Germany (7 pages). Lien externe
Bany Hamad, G., Kazma, G., Mohamed, O. A., & Savaria, Y. (novembre 2016). Efficient and accurate analysis of single event transients propagation using SMT-based techniques [Communication écrite]. 35th International Conference on Computer-Aided Design (ICCAD 2016), Austin, TX (7 pages). Lien externe
Benacer, I., Boyer, F.-R., Bélanger, N., & Savaria, Y. (juin 2016). A fast systolic priority queue architecture for a flow-based Traffic Manager [Communication écrite]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Lien externe
Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (septembre 2016). SMT-based reliability-aware synthesis for single event transients tolerant combinational circuits [Affiche]. Radiation Effects on Components & Systems Conference (RADECS 2016), Bremen, Germany. Non disponible
Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (mai 2016). Towards formal abstraction, modeling, and analysis of single event transients at RTL [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. Lien externe
Bany Hamad, G., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (2015). Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits. Microelectronics Reliability, 55(1), 238-250. Lien externe
Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (juillet 2015). Efficient Multilevel Formal Analysis and Estimation of Design Vulnerability to Single Event Transients [Communication écrite]. 21st International On-Line Testing Symposium (IOLTS 2015), Athena Pallas, Greece (6 pages). Lien externe
Bany Hamad, G., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (juin 2014). Abstracting Single Event Transient characteristics variations due to input patterns and fan-out [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, VIC, Australia (4 pages). Lien externe
Blaquiere, Y., Basile-Bellavance, Y., Berrima, S., & Savaria, Y. (juin 2014). Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, VIC, Australia (4 pages). Lien externe
Bany Hamad, G., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (août 2014). Modeling, analyzing, and abstracting single event transient propagation at gate level [Communication écrite]. IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX, USA. Lien externe
Bany Hamad, G., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (2014). New insights into the single event transient propagation through static and TSPC logic. IEEE Transactions on Nuclear Science, 61(4), 1618-1627. Lien externe
Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (décembre 2014). Probabilistic model checking of single event transient propagation at RTL level [Communication écrite]. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France. Lien externe
Bouanen, S., Thibeault, C., Savaria, Y., Tremblay, J.-P., & Zhu, G. (octobre 2013). Fault tolerant smart transducer interface for safety-critical avionics applications [Communication écrite]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. Lien externe
Bany Hamad, G., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (septembre 2013). Investigating the impact of propagation paths and re-convergent paths on the propagation induced pulse broadening [Communication écrite]. 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2013), Oxford, United kingdom (4 pages). Lien externe
Blaquièere, Y., Savaria, Y., Basile-Bellavance, Y., Valorge, O., Lahkssassi, A., André, W., Laflamme Mayer, N., Bougataya, M., & Sawan, M. (2013). Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical signal propagation. (Demande de brevet no US20130285739). Lien externe
Baratli, K., Lakhssassi, A., Blaquière, Y., & Savaria, Y. (juin 2013). A netlist pruning tool for an electronic system prototyping platform [Communication écrite]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. Lien externe
Bany Hamad, G., Ait Mohamed, O., Rafay Hasan, S., & Savaria, Y. (mai 2012). Identification of soft error glitch-propagation paths: Leveraging SAT solvers [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. Lien externe
Boulais, E., Fantoni, J., Chateauneuf, A., Savaria, Y., & Meunier, M. (2011). Laser-induced resistance fine tuning of integrated polysilicon thin-film resistors. IEEE Transactions on Electron Devices, 58(2), 572-575. Lien externe
Bany Hamad, G., Mohamed, O. A., Hasan, S. R., & Savaria, Y. (décembre 2011). SEGP-finder: Tool for identification of soft error glitch-propagating paths at gate level [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Berriah, O., Bougataya, M., Lakhssassi, A., Blaquiere, Y., & Savaria, Y. (juin 2010). Thermal analysis of a miniature electronic power device matched to a silicon wafer [Communication écrite]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. Lien externe
Bougataya, M., Berriah, O., Lakhssassi, A., Dahmane, A.-O., Blaquiere, Y., Savaria, Y., Norman, R., & Prytula, R. (décembre 2010). Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit [Communication écrite]. 17th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece. Lien externe
Basile-Bellavance, Y., Blaquiere, Y., & Savaria, Y. (juin 2009). Faults diagnosis methodology for the WaferNet interconnection network [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Bafumba-Lokilo, D., Savaria, Y., & David, J. P. (octobre 2009). Generic array-based MPSoC architecture [Communication écrite]. 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada. Lien externe
Beucher, N., Belanger, N., Savaria, Y., & Bois, G. (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), 155-165. Lien externe
Bui, H. T., & Savaria, Y. (2008). Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-Ghz Frequency-Locked Loop. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(3), 766-774. Lien externe
Bafumba-Lokilo, D., Savaria, Y., & David, J. P. (juin 2008). Generic crossbar network on chip for FPGA MPSoCs [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Basile-Bellavance, Y., Lepercq, E., Blaquiere, Y., & Savaria, Y. (août 2008). Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL [Communication écrite]. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008). Lien externe
Bouyela Ngoyi, G.-A., Langlois, J. M. P., & Savaria, Y. (juin 2008). Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Bougataya, M., Lakhsasi, A., Norman, R., Prytula, R., Blaquière, Y., & Savaria, Y. (mai 2008). Steady state thermal analysis of a reconfigurable wafer-scale circuit board [Communication écrite]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008), Niagara Falls, Ont.. Lien externe
Boulais, É., Binet, V., Degorce, J.-Y., Wild, G., Savaria, Y., & Meunier, M. (2008). Thermodynamics and Transport Model of Charge Injection in Silicon Irradiated by a Pulsed Focused Laser. IEEE Transactions on Electron Devices, 55(10), 2728-2735. Lien externe
Benamrane, I., & Savaria, Y. (août 2007). Design techniques for high speed current steering DACs [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montreal, Qc, Canada (4 pages). Lien externe
Blaquiere, Y., Savaria, Y., & El Fouladi, J. (décembre 2007). Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os [Communication écrite]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco (4 pages). Lien externe
Binet, V., Savaria, Y., Meunier, M., & Gagnon, Y. (mai 2007). Modeling the substrate noise injected by a DC-DC converter [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), Phoenix-Scottsdale, AZ. Lien externe
Boyer, F.-R., Epassa, H. G., & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290. Lien externe
Bui, H. T., & Savaria, Y. (avril 2006). High speed differential pulse-width control loop based on frequency-to-voltage converters [Communication écrite]. 16th ACM Great Lakes Symposium on VLSI (GLSVLSI 2006), Philadelphia, USA. Lien externe
Beucher, N., Belanger, N., Savaria, Y., & Bois, G. (octobre 2006). Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor [Communication écrite]. IEEE Workshop on Signal Processing Systems Design and Implementation, Banff, AB, Canada. Lien externe
Belanger, N., & Savaria, Y. (juin 2006). On the design of a double precision logarithmic number system arithmetic unit [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Bui, H. T., & Savaria, Y. (juillet 2005). Design and analysis of XOR gates for high-speed and low-jitter applications [Communication écrite]. 9th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2005), Orlando, Floride. Non disponible
Bui, H. T., & Savaria, Y. (juillet 2005). A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in Socs [Communication écrite]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. Lien externe
Bui, H. T., & Savaria, Y. (juin 2005). High-speed differential frequency-to-voltage converter [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005). Lien externe
Bui, H. T., & Savaria, Y. (juillet 2004). 10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 mu m CMOS [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. Lien externe
Boland, J. F., Chureau, A., Thibeault, C., Savaria, Y., Gagnon, F., & Zilic, Z. (juin 2004). An efficient methodology for design and verification of an equalizer for a software defined radio [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Boudjella, A., Jin, Z., & Savaria, Y. (2004). Electrical Field Analysis of Nanoscale Field Effect Transistors. Japanese Journal of Applied Physics, 43(6), 3831-3837. Lien externe
Bui, H. T., & Savaria, Y. (mai 2004). Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. Lien externe
Bui, T., & Savaria, Y. (juin 2004). Shunt-peaking of MCML gates using active inductors [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Bougataya, M., Lakhasasi, A., Savaria, Y., & Massicotte, D. (mai 2004). Thermo-mechanical stress analysis of VLSI devices by partially coupled finite element method [Communication écrite]. 18th Annual Canadian Conference on Electrical and Computer Engineering (CCEC 2004), Niagara Falls, Ontario. Lien externe
Boyer, F.-R., Epassa, H. G., Pontikakis, B., Savaria, Y., & Ling, W. (juin 2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Bissou, J. P., & Savaria, Y. (janvier 2003). Conception de haut niveau d'une plate-forme SOC pour la conversion de protocoles réseaux [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). Lien externe
Beaudin, S., Marceau, R. J., Bois, G., Savaria, Y., & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112. Lien externe
Boudjella, A., Jin, Z.-F., & Savaria, Y. (octobre 2003). Electrical field analysis of nanoscaled field effect transistors [Communication écrite]. International Microprocesses and Nanotechnology Conference, Tokyo, Japan. Lien externe
Bissou, J. P., Dubois, M., Savaria, Y., & Bois, G. (décembre 2003). High-speed system bus for a SoC network processing platform [Communication écrite]. 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt. Lien externe
Bougataya, M., Lakhsasi, A., Savaria, Y., & Massicotte, D. (janvier 2003). Stress and distortion behavior for VLSI steady state thermal analysis [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). Lien externe
Bendali, A., & Savaria, Y. (mai 2002). Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. Lien externe
Boyer, F.-R., Aboulhamid, E. M., & Savaria, Y. (août 2001). Minimizing sensitivity to clock skew variations using level sensitive latches [Communication écrite]. 15th European Conference on Circuit Theory and Design (ECCTD 2001), Espoo, Finland. Non disponible
Boyer, F.-R., Aboulhamid, E. M., Savaria, Y., & Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), 516-532. Lien externe
Boyer, F.-R., Aboulhamid, E. M., & Savaria, Y. (janvier 2000). Efficient verification method for a class of multi-phase sequential circuits [Communication écrite]. 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000). Lien externe
Bosi, B., Bois, G., & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308. Lien externe
Boyer, F.-R., Abiylhamid, E. M., Savaria, Y., & Bennour, I. E. (octobre 1998). Optical design of synchronous circuits using software pipeling techniques [Communication écrite]. VLSI in Computers and Processors, Austin, TX, USA. Lien externe
Bélanger, N., Antaki, B., & Savaria, Y. (juillet 1997). An algorithm for fast array transfers [Communication écrite]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Non disponible
Bois, G., Bosi, B., & Savaria, Y. (janvier 1997). High performance reconfigurable coprocessor for digital signal processing [Communication écrite]. 14th Annual International Conference of the Mentor Graphics Users' Group, Portland, Oregon. Non disponible
Belabbes, N.-E., Guterman, A. J., Savaria, Y., & Dagenais, M. (1996). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(2), 143-152. Lien externe
Belhaouane, A., Savaria, Y., & Kaminska, B. (janvier 1996). Reconstruction method for data acquisition systems with randomly distributed jitter [Communication écrite]. 2nd IEEE International Mixed Signal Testing Workshop. Non disponible
Belhaouane, A., Savaria, Y., Kaminska, B., & Massicotte, D. (1996). Reconstruction method for jitter tolerant data acquisition system. Journal of Electronic Testing: Theory and Applications, 9(1-2), 177-185. Lien externe
Blaquiere, Y., Dagenais, M., & Savaria, Y. (1996). Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), 244-255. Lien externe
Barwicz, A., Massicotte, D., Savaria, Y., Pango, P. A., & Morawski, R. Z. (1995). An application-specific processor dedicated to kalman-filter-based correction of spectrometric data. IEEE Transactions on Instrumentation and Measurement, 44(3), 720-724. Lien externe
Belzile, J., Savaria, Y., Haccoun, D., & Chalifoux, M. (1995). Bounds on the performance of partial selection networks. IEEE Transactions on Communications, 43(2-4), 1800-1809. Lien externe
Blaquiere, T., Gagné, G., Savaria, Y., & Évéquoz, C. (1995). A new efficient algorithmic-based seu tolerant system architecture. IEEE Transactions on Nuclear Science, 42(6), 1599-1606. Lien externe
Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M.-A., & Morawski, R. Z. (mai 1994). An application-specific processor dedicated to Kalman-filter-based correction of spectrometric data [Communication écrite]. IEEE Instrumentation and Measurement Technology Conference (IMTC 1994), Hamamatsu, Japan. Lien externe
Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M. A., & Morawski, R. Z. (1994). An integrated structure for kalman-filter-based measurand reconstruction. IEEE Transactions on Instrumentation and Measurement, 43(3), 403-410. Lien externe
Bélanger, N., Haccoun, D., & Savaria, Y. (1994). A multiprocessor architecture for multiple path stack sequential decoders. IEEE Transactions on Communications, 42(2-4, pt.2), 951-957. Lien externe
BenHamida, N., Kaminska, B., & Savaria, Y. (mai 1994). Pseudo-random vector compaction for sequential testability [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
Belabbes, N., Guterman, A., Savaria, Y., & Dagenais, M. (mai 1992). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
Blaquiere, Y., & Savaria, Y. (1987). Area Overhead Analysis of SEF: A Design Methodology for Tolerating SEU. IEEE Transactions on Nuclear Science, 34(6), 1481-1486. Lien externe
Chebli, R., Sawan, M., El-Sankary, K., & Savaria, Y. (2010). High-voltage DMOS integrated circuits using floating-gate protection technique. Analog Integrated Circuits and Signal Processing, 62(2), 223-235. Lien externe
Chebli, R., Sawan, M., Savaria, Y., & El-Sankary, K. (mai 2007). High-voltage DMOS integrated circuits with floating gate protection technique [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, USA. Lien externe
Castonguay, A., & Savaria, Y. (mai 2006). Architecture of a hypertransport tunnel [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. Lien externe
Chureau, A., Savaria, Y., Boland, J.-F., Zilic, Z., Thibeault, C., & Gagnon, F. (juin 2006). Building heterogeneous functional prototypes using articulated interfaces [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Chebli, R., Sawan, M., & Savaria, Y. (août 2006). High-Voltage CMOS/DMOS Interface dedicated for ultrasonic sensing [Communication écrite]. International Workshop on Computer Architecture for Machine Perception and Sensing (CAMP 2006), Montréal, Québec. Lien externe
Cantin, M.-A., Savaria, Y., Prodanos, D., & Lavoie, P. (2006). A metric for automatic word-length determination of hardware datapaths. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10), 2228-31. Lien externe
Chebli, R., Sawan, M., & Savaria, Y. (décembre 2005). Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results [Communication écrite]. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2005), Tunisie. Lien externe
Castonguay, A., & Savaria, Y. (juin 2005). A Hypertransport Chip-to-Chip Interconnect Tunnel Developed Using Systemc [Communication écrite]. 16th International Workshop on Rapid System Prototyping, Montréal, Québec. Lien externe
Catudal, S., Cantin, M. A., & Savaria, Y. (mai 2005). Parameters Estimation Applied to Automatic Video Processing Algorithms Validation [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Chebli, R., Sawan, M., & Savaria, Y. (août 2005). A programmable positive and negative high-voltage DC-DC converter dedicated for ultrasonic applications [Communication écrite]. 48th Midwest Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio. Lien externe
Chureau, A., Savaria, Y., & Aboulhamid, E. M. (mars 2005). The Role of Model-Level Transactors and Uml in Functional Prototyping of Systems-on-Chip: a Software-Radio Application [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2005), Munich, Germany. Lien externe
Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. (2005). Scheduling and Optimal Register Placement for Synchronous Circuits Derived Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 10(2), 187-204. Lien externe
Calbaza, D. E., Cordos, I., Seth-Smith, N., & Savaria, Y. (mai 2004). An Adpll Circuit Using a Ddps for Genlock Applications [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2004). Lien externe
Cantin, M. A., Savaria, Y., & Velazco, R. (2004). An automatic word length determination method. WSEAS Transactions on Information Science & Applications, 1(5), 1440-1448. Non disponible
Chureau, A., Savaria, Y., & Aboulhamid, E. M. (juillet 2004). Interface-based design of systems-on-chip using UML-RT [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. Lien externe
Catudal, S., Cantin, M.-A., & Savaria, Y. (2004). Performance driven validation applied to video processing. WSEAS Transactions on Electronics, 1(3), 568-575. Non disponible
Cantin, M. A., Regimbal, S., Catudal, S., & Savaria, Y. (2004). A Unified Environment to Assess Image Quality in Video Processing. Journal of Circuits, Systems and Computers, 13(6), 1289-1306. Lien externe
Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003). Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), 346-351. Lien externe
Catudal, S., Cantin, M. A., & Savaria, Y. (2003). Performance driven validation applied to viseo processing. WSEAS Transactions on Electronics, 1(3), 568-574. Non disponible
Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (avril 2003). Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs [Communication écrite]. Great Lakes Symposium on VLSI (GLSVLSI 2003), Washington, D. C., USA. Lien externe
Cantin, M.-A., Savaria, Y., & Lavoie, P. (mai 2002). A comparison of automatic word length optimization procedures [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. Lien externe
Calbaza, D. E., & Savaria, Y. (2002). A Direct Digital Period Synthesis Circuit. IEEE Journal of Solid-State Circuits, 37(8), 1039-1045. Lien externe
Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. Minimizing the Number of Phases in Clocked Digital Designs Derived Using Modulo Scheduling Techniques [Communication écrite]. Icm 2002: 14th International Conference on Microelectronics. Lien externe
Cantin, M.-A., Savaria, Y., Prodanos, D., & Lavoie, P. (mai 2001). An automatic word length determination method [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, NSW, Australia. Lien externe
Chabini, N., Aboulhamid, M., & Savaria, Y. (janvier 2001). Determining schedules for reducing power consuption using mulyiple supply voltages [Communication écrite]. International Conference on Computer Design (ICCD 2001), Austin, Texas. Lien externe
Calbaza, D. E., & Savaria, Y. (2001). Direct Digital Frequency Synthesis of Low-Jitter Clocks. IEEE Journal of Solid-State Circuits, 36(3), 570-572. Lien externe
Chabini, N., Aboulhamid, M., & Savaria, Y. (janvier 2001). Efficient methods for reducing register and phase requirements for synchronous circuits derived using software pipeling techniques [Communication écrite]. European Conference on Circuit Theory and Design, Espoo, Finland. Non disponible
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (janvier 2001). Fast method for determining an efficient bound on the optimal solution of the cost-to-time ratio problem [Communication écrite]. 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001) and 7th International Conference in Information Systems Analysis and Synthesis (ISAS 2001), Orlando, Floride. Non disponible
Chabini, N., & Savaria, Y. (janvier 2001). Methods for optimizating register placement in synchronous circuits derived using software pipelining techniques [Communication écrite]. 14th International Symposium on System Synthesis (ISSS 2001), Montréal, Québec. Lien externe
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (janvier 2001). Minimizing registe requirements for synchronous circuits derived using software pipelining techniques [Communication écrite]. 13th International Conference on Microelectronics (ICM 2001), Rabat, Maroc. Lien externe
Chabini, N., Aboulhamid, E. M., & Savaria, Y. (avril 2001). Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques [Communication écrite]. IEEE Computer Society Workshop on VLSI (WVLSI 2001), Orlando, FL, United states. Lien externe
Cantin, M.-A., Blaquière, Y., Savaria, Y., Lavoie, P., & Granger, É. (mai 2000). Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland. Lien externe
Calbaza, D. E., & Savaria, Y. (mai 2000). Direct digital frequency synthesis of low-jitter clocks [Communication écrite]. IEEE Custom Integrated Circuits Conference, Orlando, FL, USA. Lien externe
Calbaza, D. E., & Savaria, Y. (octobre 2000). A direct digitally delay generator [Communication écrite]. 23rd International Semiconductor Conference (CAS 2000), Sinaia, Romania. Lien externe
Calbaza, D. E., & Savaria, Y. (janvier 2000). Jitter model of direct digital synthesis clock generators [Communication écrite]. TCAS-I 2000. Non disponible
Cousineau, C., Laperle, F., Savaria, Y., Pocek, K. L., & Arnold, J. M. (avril 1999). Design of a JTAG based run time reconfigurable system [Communication écrite]. 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA. Lien externe
Calbaza, D. E., & Savaria, Y. (mai 1999). Jitter model of direct digital synthesis clock generators [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. Lien externe
Cantin, M.-A., Blaquière, Y., Savaria, Y., Granger, É., & Lavoie, P. (mai 1998). Implementation fo the Fuzzy ART neural network for fast clustering of radar pulses [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1998), Monterey, CA, USA. Lien externe
Chabini, N., Bennour, I. E., Aboulhamid, E. M., & Savaria, Y. (janvier 1998). Static method for system performance estimation [Communication écrite]. 10th International Conference on Microelectronics. Lien externe
Crespo, J.-F., Lavoie, P., & Savaria, Y. (mai 1994). Fast convergence with low precision weights in ART1 networks [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
Crépeau, J., Thibeault, C., & Savaria, Y. (octobre 1993). Some results on yield and local design rule relaxation [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1993), Venice, Italy. Lien externe
Currie, J. F., Savaria, Y., & Dionne, J.-P. (1988). Réalisation d'un diviseur de fréquence numérique sur AsGa. (Rapport technique n° EPM-RT-88-03). Accès restreint
Dufour, J., Savaria, Y., & David, J. P. Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries [Communication écrite]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). Lien externe
Dupuis, T., Fournier, Y., AskariHemmat, M.H., Zarif, N. E., Leduc-Primeau, F., David, J. P., & Savaria, Y. (juin 2023). Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference [Communication écrite]. 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). Lien externe
Deca, R., Cherkaoui, O., & Savaria, Y. (septembre 2014). Constraint-based configuration complexity model for autonomic network configuration management [Communication écrite]. Global Information Infrastructure and Networking Symposium (GIIS 2014), Montréal, Québec. Lien externe
Deca, R., Cherkaoui, O., & Savaria, Y. (2012). Rule-based network service provisioning. Journal of Networks, 7(10), 1493-1504. Lien externe
Deca, R., Cherkaoui, O., Savaria, Y., & Slone, D. (2007). Constraint-Based Model Service for Network Provisioning. Annales des télécommunications, 62(7-8), 847-870. Lien externe
Dubois, M., Savaria, Y., Haccoun, D., & Belanger, N. (2006). Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders. IEE Proceedings. Circuits, Devices and Systems, 153(3), 207-213. Lien externe
Deslauriers, F., Langevin, M., Bois, G., Savaria, Y., & Paulin, P. (juin 2006). RoC: a scalable network on chip based on the token ring concept [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Deca, R., Mahrez, O., Cherkaoui, O., Savaria, Y., & Slone, D. (août 2005). Contributions to automated testing of network service interactions [Communication écrite]. 5e Colloque International sur les nouvelles technologies de la répartition (NOTERE 2005), Gatineau, Québec. Non disponible
Dubois, M., Savaria, Y., & Bois, G. (avril 2005). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands [Communication écrite]. IEEE SoutheastCon 2004, Fort Lauderdale, Florida, USA. Lien externe
Dang, H., Sawan, M., & Savaria, Y. (mai 2005). A Novel Approach for Implementing Ultra-High Speed Flash Adc Using Mcml Circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Dubois, M., Bois, G., & Savaria, Y. (2004). Double profiling methodology for video processing platform. WSEAS Transactions on Computers, 3(6), 1802-1807. Non disponible
Duval, O., Lafrance, L. P., Savaria, Y., & Desjardins, P. (août 2004). An Integrated Test Platform for Nanostructure Electrical Characterization [Communication écrite]. International Conference on Mems, Nano and Smart Systems (ICMENS 2004), Banff, Canada. Lien externe
Dubois, M., Savaria, Y., & Haccoun, D. (juin 2004). On low power shift register hardware realizations for convolutional encoders and decoders [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Duval, O., & Savaria, Y. (mai 2004). An on-chip delay measurements module for nanostructures characterization [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. Lien externe
Dido, J., Geraudie, N., Loiseau, L., Payeur, O., Savaria, Y., & Poirier, D. (février 2002). A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs [Communication écrite]. 10th ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2002). Lien externe
Donfack, C., Sawan, M., & Savaria, Y. (janvier 2000). Fully integrated AC impedance measurement technique for implantable electrical stimulation applications [Communication écrite]. 5th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 2000), Denmark. Non disponible
Donfack, C., Sawan, M., & Savaria, Y. (2000). Implantable Measurement Technique Dedicated to the Monitoring of Electrode-Nerve Contact in Bladder Stimulators. Medical & Biological Engineering & Computing, 38(4), 465-468. Lien externe
Donfack, C., Sawan, M., & Savaria, Y. (janvier 2000). Techniques de caractérisation de l'interface électrode-tissus [Communication écrite]. 2nd Symposium on Advanced Biomaterials (ISAB 2000), Montréal, Québec. Non disponible
Donfack, C., Sawan, M., & Savaria, Y. (janvier 1999). Efficient monitoring of electrodes-nerve contacts during FNS of the bladder [Communication écrite]. 4th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 1999), Sendai, Japon. Non disponible
Dahmani, A., Savaria, Y., & Kaminska, B. (mai 1992). Standard cell placement with Dynamic Clouds method [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
El Zarif, N., Hemmat, M. A., Dupuis, T., David, J. P., & Savaria, Y. (2024). Polara-Keras2c: Supporting Vectorized AI Models on RISC-V Edge Devices. IEEE Access, 12, 171836-171852. Lien externe
Ehmer, J., Savaria, Y., Granado, B., David, J. P., & Denoulet, J. (2024). Network Attack Classification with a Shallow Neural Network for Internet and Internet of Things (IoT) Traffic. Electronics, 13(16), 3318-3318. Lien externe
El-Zarif, N., Amer, M., Ali, M., Hassan, A., Oukaira, A., Fayomi, C., & Savaria, Y. (2024). Calibration of ring oscillator-based integrated temperature sensors for power management systems. Sensors, 24(2), 440 (17 pages). Disponible
Elbediwy, M., Pontikakis, B., David, J.‐P., & Savaria, Y. (2024). Enabling Rank-Based P4 Programmable Schedulers: Requirements, Implementation, and Evaluation on BMv2 Switches. IEEE/ACM Transactions on Networking, 1-12. Lien externe
El-Zarif, N., Fayomi, C., Ali, M., Amer, M., Hassan, A., & Savaria, Y. (2024). A Systematic Approach for PLL-based Zeta Power Converter Control. IEEE Access, 1-1. Lien externe
Elbediwy, M., Pontikakis, B., Ghaffari, A., David, J. P., & Savaria, Y. (2024). DR-PIFO: a dynamic ranking packet scheduler using a push-in-first-out queue. IEEE Transactions on Network and Service Management, 21(1), 355-371. Lien externe
Elbediwy, M., Pontikakis, B., David, J. P., & Savaria, Y. (2023). A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access, 11, 61422-61436. Disponible
El-Zarif, N., Ali, M., Amer, M., Hassan, A., Oukaira, A., Lakhssassi, A., Fayomi, C. J. B., & Savaria, Y. (juin 2022). Investigation of Different Integrated Temperature Monitoring Sensors for High-Voltage SoC DC-DC Converters [Communication écrite]. 20th IEEE International Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, QC, Canada. Lien externe
Ehmer, J., Granado, B., Denoulet, J., Savaria, Y., & David, J. P. (juin 2022). Low complexity shallow neural network with improved false negative rate for cyber intrusion detection systems [Communication écrite]. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada. Lien externe
Eddine, T. D., Oukaira, A., Hassan, A., Savaria, Y., & Lakhssassi, A. (juin 2021). Foster-based Transient Thermal Analysis of SiP for Thermomechanical Studies [Communication écrite]. 19th IEEE International New Circuits and Systems Conference (NEWCAS 2021), Toulon, France (4 pages). Lien externe
Ettahri, O., Oukaira, A., Ali, M., Hassan, A., Nabavi, M., Savaria, Y., & Lakhssassi, A. (2020). A Real-Time Thermal Monitoring System Intended for Embedded Sensors Interfaces. Sensors, 20(19), 5657 (16 pages). Disponible
El-Zarif, N., Ali, M., Hassan, A., Nabavi, M., Fayomi, C. J. B., & Savaria, Y. (février 2020). A High Efficiency and Fast Response PLL Based Buck Converter: Implementation and Simulation [Communication écrite]. IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS 2020), San Jose, Costa Rica (4 pages). Lien externe
El Fouladi, J., Lu, Z., Savaria, Y., & Martel, S. (août 2007). An integrated biosensor for the detection of bio-entities using magnetotactic bacteria and CMOS technology. [Communication écrite]. 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2007), Lyon, France. Lien externe
El fouladi, J., André, W., Savaria, Y., & Martel, S. (août 2006). System design of an integrated measurement electronic subsystem for bacteria detection using and electrode array and MC-1 magnetotactic bacteria [Communication écrite]. International Workshop on Computer Architecture for Machine Perception and Sensing (CAMP 2006), Montréal, Québec. Lien externe
Epassa, H. G., Boyer, F.-R., & Savaria, Y. (mai 2005). Implementation of a Cycle by Cycle Variable Speed Processor [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Faraji, A., Sadrossadat, S. A., Moftakharzadeh, A., Nabavi, M., & Savaria, Y. (2023). Deep Independent Recurrent Neural Network Technique for Modeling Transient Behavior of Nonlinear Circuits. IEEE Transactions on Components, Packaging and Manufacturing Technology, 13(5), 688-699. Lien externe
Faraji, A., Sadrossadat, S. A., Yazdian-Dehkordi, M., Nabavi, M., & Savaria, Y. (2022). A Hybrid Approach Based on Recurrent Neural Network for Macromodeling of Nonlinear Electronic Circuits. IEEE Access, 10, 127996-128006. Lien externe
Fiorentino, M., Thibeault, C., & Savaria, Y. (2021). Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow. IET Computers & Digital Techniques, 15(6), 409-426. Disponible
Foroushani, A. N., Assaf, H., Noshahr, F. H., Savaria, Y., & Sawan, M. (octobre 2020). Analog circuits to accelerate the relaxation process in the equilibrium propagation algorithm [Communication écrite]. 52nd IEEE International Symposium on Circuits and Systems (ISCAS 2020) (5 pages). Lien externe
Fiorentino, M., Thibeault, C., Savaria, Y., Gagnon, F., Awad, T., Morrissey, D., & Laurence, M. (mai 2019). AnARM: a 28nm energy efficient ARM processor based on Octasic asynchronous technology [Communication écrite]. 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan. Lien externe
Fradj, B., Wolff, B., Bélanger, N., & Savaria, Y. (mai 2018). Implementation of a cache-based IPv6 lookup system with hashing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (4 pages). Lien externe
Fiorentino, M., Savaria, Y., & Thibeault, C. (juin 2017). FPGA implementation of Token-based Self-timed processors: A case study [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Fiorentino, M., Savaria, Y., Thibeault, C., & Gervais, P. (mai 2016). A practical design method for prototyping self-timed processors using FPGAs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. Lien externe
Fiorentino, M., Al-Terkawi, O., Savaria, Y., & Thibeault, C. (juin 2015). Self-timed circuits FPGA implementation flow [Communication écrite]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Lien externe
Farah, R., Gan, Q., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (2014). A computationally efficient importance sampling tracking algorithm. Machine Vision and Applications, 25(7), 1761-1777. Lien externe
Fischer, A., Plamondon, R., Savaria, Y., Riesen, K., & Bunke, H. (août 2014). A Hausdorff heuristic for efficient computation of graph edit distance [Communication écrite]. Joint IAPR International Workshop on Structural, Syntactic, and Statistical Pattern Recognition (S+SSPR 2014), Joensuu, Finland. Lien externe
Fischer, A., Plamondon, R., O'Reilly, C., & Savaria, Y. (septembre 2014). Neuromuscular representation and synthetic generation of handwritten whiteboard notes [Communication écrite]. 14th International Conference on Frontiers in Handwriting Recognition (ICFHR 2014), Crete, Greece. Lien externe
Farah, R., Gan, Q., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (décembre 2011). A tracking algorithm suitable for embedded systems implementation [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Fouzar, Y., Savaria, Y., & Sawan, M. (mai 2002). A CMOS phase-locked loop with an auto-calibrated VCO [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. Lien externe
Fouzar, Y., Savaria, Y., & Sawan, M. (mai 2001). A new controlled gain phase-locked loop technique [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, NSW, Australia. Lien externe
Fouzar, Y., Sawan, M., & Savaria, Y. CMOS Wide-Swing Differential VCO for Fully Integrated Fast PLL [Communication écrite]. 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000). Lien externe
Fouzar, Y., Sawan, M., & Savaria, Y. (mai 2000). A new fully integrated CMOS phase-locked loop with low jitter and fast lock time [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland. Lien externe
Fouzar, Y., Sawan, M., & Savaria, Y. (décembre 2000). Very short locking time PLL based on controlled gain technique [Communication écrite]. 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000), Jounieh, Lebanon. Lien externe
Fouzar, Y., Sawan, M., & Savaria, Y. (décembre 1998). A BiCMOS wide-lock range fully integrated PLL [Communication écrite]. 10th International Conference on Microelectronics, Monastir, Tunisia. Lien externe
Ghaffari, A., Asgharian, M., & Savaria, Y. (2024). Statistical hardware design with multi-model active learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(2), 11 pages. Lien externe
Ghaffari, A., & Savaria, Y. (2021). Efficient Design Space Exploration of OpenCL Kernels for FPGA Targets Using Black Box Optimization. IEEE Access, 9, 136819-136830. Lien externe
Ghaffari, A., & Savaria, Y. (2020). CNN2Gate: an implementation of convolutional neural networks inference on FPGAs with automated design space exploration. Electronics, 9(12), 23 pages. Disponible
Ghaffari, A., Leonardon, M., Cassagne, A., Leroux, C., & Savaria, Y. (2019). Toward high-performance implementation of 5G SCMA algorithms. IEEE Access, 7, 10402-10414. Lien externe
Gemieux, M., Li, M., Savaria, Y., David, J. P., & Zhu, G. (2018). A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access, 6, 62826-62839. Lien externe
Gémieux, M., Savaria, Y., David, J. P., & Zhu, G. (mai 2017). A cache-coherent heterogeneous architecture for low latency real time applications [Communication écrite]. 20th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2017), Toronto, ON, Canada. Lien externe
Ghaffari, A., Leonardon, M., Savaria, Y., Jego, C., & Leroux, C. (juin 2017). Improving performance of SCMA MPA decoders using estimation of conditional probabilities [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Gémieux, M., Savaria, Y., Zhu, G., & Frigon, J.-F. (juin 2016). Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling [Communication écrite]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Lien externe
Guillemot, M., Nguyen, H., Bougataya, M., Blaquiere, Y., Lakhssassi, A., Shields, M., & Savaria, Y. (2016). Wafer-scale rapid electronic systems prototyping platform: User support tools and thermo-mechanical validation. Dans Novel Advances in Microsystems Technologies and Their Applications (p. 67-100). Lien externe
Gan, Q. F., Langlois, J. M. P., & Savaria, Y. (2014). Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations. Journal of Signal Processing Systems for Signal Image and Video Technology, 75(3), 191-202. Lien externe
Gan, Q., Langlois, J. M. P., & Savaria, Y. (2014). A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems. Circuits, Systems & Signal Processing, 33(11), 3591-3602. Lien externe
Gill, D. C., Langlois, J. M. P., & Savaria, Y. (octobre 2013). Accelerating a modified gaussian pyramid with a customized processor [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2013), Cagliari, Italy. Lien externe
Gan, Q., Langlois, J. M. P., & Savaria, Y. (2013). Parallel array histogram architecture for embedded implementations. Electronics Letters, 49(2), 99-101. Lien externe
Gan, Q., Langlois, J. M. P., & Savaria, Y. (août 2013). A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor [Communication écrite]. 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2013), Columbus, OH, USA. Lien externe
Guillemot, M., Blaquière, Y., & Savaria, Y. (mai 2013). Software Rendering Methods to Display Wafer Scale Integrated Circuit Dataset [Communication écrite]. 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2013), Regina, Sask, CAN. Lien externe
Gil, D. C., Farah, R., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (mai 2011). Comparative analysis of contrast enhancement algorithms in surveillance imaging [Communication écrite]. IEEE International Symposium of Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil. Lien externe
Gagnon, F., Savaria, Y., Dumais, P., Ammari, M. L., & Thibeault, C. (2010). Multiequalizer unit used for telecommunications has decision unit, which receives corresponding synchronized signals and choose one synchronized signal that matches with predetermined transmission performance criterion signal. (Brevet no US7693490). Lien externe
Gorse, N., Belanger, P., Chureau, A., Aboulhamid, E. M., & Savaria, Y. (2007). A High-Level Requirements Engineering Methodology for Electronic System-Level Design. Computers & Electrical Engineering, 33(4), 249-268. Lien externe
Grou-Szabo, R., Ghattas, H., Savaria, Y., & Nicolescu, G. (juillet 2005). Component-Based Methodology for Hardware Design of a Dataflow Processing Network [Communication écrite]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. Lien externe
Gorse, N., Aboulhamid, E. M., & Savaria, Y. (juillet 2004). Consistency validation of high-level requirements [Communication écrite]. 4th International Workshop on System on Chip for Real Time Applications (IWSOC 2004), Banff, AB, Canada. Lien externe
Gorse, N., Metzger, M., Lapalme, J., Aboulhamid, E. M., Savaria, Y., & Nicolescu, G. (décembre 2004). Enhancing ESys.Net with a semi-formal verification layer [Communication écrite]. 16th International Conference on Microelectronics (ICM 2004), Tunisie. Lien externe
Gorse, N., Bélanger, P., Aboulhamid, E. M., & Savaria, Y. (décembre 2004). Mixing linguistic and formal techniques for high-level requirements engineering [Communication écrite]. 16th International Conference on Microelectronics (ICM 2004), Tunisie. Lien externe
Granger, E., Catudal, S., Grou, R., Mbaye, M. M., & Savaria, Y. (septembre 2004). On current strategies for hardware acceleration of digital image restoration filters [Communication écrite]. 4th WSEAS International Conference on Signal, Speech and Image Processing (ICOSSIP 2004), Izmir, Turquie. Lien externe
Ghattas, H., & Savaria, Y. (janvier 2003). Design of dedicated low complexity embedded processors for SOC network processing applications [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Granger, E., Catudal, S., Grou, R., Mbaye, M. M., & Savaria, Y. (2003). On current strategies for hardware acceleration of digital image restoration filters. WSEAS Transactions on Electronics, 1(3), 551-557. Non disponible
Granger, E., Savaria, Y., & Lavoie, P. (2003). A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. IEEE Transactions on Pattern Analysis and Machine Intelligence, 25(4), 524-528. Lien externe
Ghattas, H., Mbaye, M. M., Pepga, J. B., & Savaria, Y. (novembre 2003). SoC platform architecture for a network processor [Communication écrite]. International Symposium on System-on-Chip, Tampere, Finland. Lien externe
Granger, É., Savaria, Y., & Lavoie, P. (2002). A pattern reordering approach based on ambiguity detection for on-line category learning. (Rapport technique n° EPM-RT-2001-02). Disponible
Gagnon, Y., Meunier, M., & Savaria, Y. (2001). Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source. (Brevet no US6329272). Lien externe
Granger, É., Savaria, Y., Lavoie, P., & Cantin, M. A. (1998). Comparison of Self-Organizing Neural Networks for Fast Clustering of Radar Pulses. Signal Processing, 64(3), 249-269. Lien externe
Gagnon, Y., Savaria, Y., Meunier, M., & Thibeault, C. (octobre 1997). Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1997), Paris, Fr. Lien externe
Gagnon, Y., Meunier, M., Savaria, Y., & Thibeault, C. (octobre 1997). Mathematical cost model for redundant multi-processor arrays [Communication écrite]. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Publié dans Journal of Microelectronic Systems Integration, 5(4). Non disponible
Granger, É., Savaria, Y., Blaquière, Y., Cantin, M.-A., & Lavoie, P. (1997). A VLSI architecture for fast clustering with fuzzy ART neural networks. Journal of Microelectronic Systems Integration, 5(1), 3-18. Non disponible
Granger, É., Blaquière, Y., Savaria, Y., Cantin, M.-A., & Lavoie, P. (août 1996). VLSI architecture for fast clustering with fuzzy ART neural networks [Communication écrite]. 1st International Workshop on Neural Networks for Identification, Control, Robotics, and Signal/Image Processing (NICROSP 1996), Venice, Italy. Lien externe
Gadiri, A., Savaria, Y., & Kaminska, B. (septembre 1995). Optimized CMOS compatible photoreceiver [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, QC, Canada. Lien externe
Ghannoum, S., Chtchvyrkov, D., & Savaria, Y. (mai 1994). Comparative study of single-phase clocked latches using estimation criteria [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
Ghannoum, S., Chtchvyrkov, D., & Savaria, Y. (août 1994). Single-clock dynamic latches optimization [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Humblet, E., Dupuis, T., Fournier, Y., AskariHemmat, M. H., Leduc-Primeau, F., David, J. P., & Savaria, Y. (août 2024). MSPARQ: A RISC-V Vector Processor Array Optimized for Low-Resolution Neural Networks [Communication écrite]. IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS 2024), Springfield, MA, USA. Lien externe
Hassan, A., Trigui, A., Savaria, Y., & Sawan, M. (septembre 2023). High-Temperature Fully Integrated Wireless Monitoring Systems for Aerospace Applications [Communication écrite]. IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE 2023), Aveiro, Portugal. Lien externe
Hassan, A., Noël, J.-P., Savaria, Y., & Sawan, M. (2022). Circuit Techniques in GaN Technology for High-Temperature Environments. Electronics, 11(1), 22 pages. Lien externe
Hoque, M. U., Kumar, D., Audet, Y., & Savaria, Y. (2022). Design and Analysis of a 35 GHz Rectenna System for Wireless Power Transfer to an Unmanned Air Vehicle. Energies, 15(1), 19 pages. Lien externe
Hammoud, A., Assaf, H., Savaria, Y., Nguyen, D. K., & Sawan, M. (2022). A Molecular Imprinted PEDOT CMOS Chip-based Biosensor for Carbamazepine Detection. IEEE Transactions on Biomedical Circuits and Systems, 16(1), 15-23. Lien externe
Hassan, A., Amer, M., Savaria, Y., & Sawan, M. (2020). Fully Integrated Digital GaN-based LSK Demodulator for High-Temperature Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(9), 1579-1583. Disponible
Henwood, S., Leduc-Primeau, F., & Savaria, Y. (août 2020). Layerwise noise maximisation to train low-energy deep neural networks [Communication écrite]. 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020), Genova, Italy. Lien externe
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2020). Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. Journal of Electronic Testing-Theory and Applications, 35(6), 823-838. Lien externe
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2020). Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(3), 764-776. Lien externe
Hassan, A., Amer, M., Savaria, Y., & Sawan, M. (juin 2020). Towards GaN500-based high temperature ICs: Characterization and modeling up to 600°C [Communication écrite]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Qc, Canada. Lien externe
Hassan, A., Ali, M., Trigui, A., Savaria, Y., & Sawan, M. (2019). A GaN-based wireless monitoring system for high-temperature applications. Sensors, 19(8), 1785 (17 pages). Disponible
Hassan, A., Ali, M., Savaria, Y., & Sawan, M. (2019). GaN-based LSK demodulators for wireless data receivers in high-temperature applications. Microelectronics Journal, 84, 129-135. Disponible
Hoque, K. A., Ait Mohamed, O., & Savaria, Y. (2019). Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs. Reliability Engineering and System Safety, 182, 107-119. Lien externe
Hassan, A., Savaria, Y., & Sawan, M. (2018). Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 2085-2098. Disponible
Hasib, O. A.-T., Crepeau, D., Awad, T., Dulipovici, A., Savaria, Y., & Thibeault, C. (avril 2018). Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits [Communication écrite]. 36th IEEE VLSI Test Symposium (VTS 2018), Los Alamitos, CA (6 pages). Lien externe
Hassan, A., Savaria, Y., & Sawan, M. (2018). GaN Integration Technology, an Ideal Candidate for High-Temperature Applications: A Review. IEEE Access, 6, 78790-78802. Lien externe
Hoque, K. A., Ait Mohamed, O., & Savaria, Y. (2017). Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications. Journal of Applied Logic, 25(47-68), 47-68. Lien externe
Hoque, F., Savaria, Y., & Cardinal, C. (avril 2017). Joint power control and beamformer design with antenna selection [Communication écrite]. 30th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2017), Windsor, ON, Canada. Lien externe
Hassan, A., Ali, M., Trigui, A., Hached, S., Savaria, Y., & Sawan, M. (juin 2017). Stability of GaN150-based HEMT in high temperature up to 400°C [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Hoque, K. A., Mohamed, O. A., & Savaria, Y. (avril 2016). Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience [Communication écrite]. Annual IEEE Systems Conference (SysCon 2016), Orlando, Flordia (6 pages). Lien externe
Hussain, W., Fakhoury, H., Desgreys, P., Blaquiere, Y., & Savaria, Y. (2016). An asynchronous delta-modulator based A/D converter for an electronic system prototyping platform. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(6), 751-762. Lien externe
Hussain, W., Savaria, Y., & Blaquiere, Y. (mai 2016). A compact spatially configurable differential input stage for a field programmable interconnection network [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. Lien externe
Hussain, W., Valorge, O., Blaquiere, Y., & Savaria, Y. (2016). A novel spatially configurable differential interface for an electronic system prototyping platform. Integration, the VLSI Journal, 55, 129-137. Lien externe
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (avril 2016). WeSPer: a flexible small delay defect quality metric [Communication écrite]. 34th IEEE VLSI Test Symposium (VTS 2016), Las Vegas, Nevada (6 pages). Lien externe
Hassan, A., Trigui, A., Shafique, U., Savaria, Y., & Sawan, M. (mai 2016). Wireless power transfer through metallic barriers enclosing a harsh environment, feasibility and preliminary results [Affiche]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. Lien externe
Hussain, W., Blaquiere, Y., & Savaria, Y. (2015). An interface for open-drain bidirectional communication in field programmable interconnection networks. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(10), 2465-2475. Lien externe
Hoque, K. A., Mohamed, O. A., & Savaria, Y. (mars 2015). Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2015), Grenoble, France. Lien externe
Hoque, K. A., Mohamed, O. A., Savaria, Y., & Thibeault, C. (octobre 2014). Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications [Communication écrite]. 12th ACM/IEEE International Conference on Methods and Models for System Design (MEMOCODE 2014), Lausanne, Switzerland. Lien externe
Hoque, K. A., Ait Mohamed, O., Savaria, Y., & Thibeault, C. (octobre 2013). Early analysis of soft error effects for aerospace applications using probabilistic model checking [Communication écrite]. 2nd International Workshop of Formal Techniques for Safety-Critical Systems (FTSCS 2013), Queenstown, New Zealand. Lien externe
Hussain, W., Savaria, Y., & Blaquière, Y. (mai 2013). An interface for the I2C protocol in the WaferBoard TM [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, Chine. Lien externe
Hashemi, S. S., Sawan, M., & Savaria, Y. (2012). A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices. IEEE Transactions on Biomedical Circuits and Systems, 6(4), 326-335. Lien externe
Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2011). All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. Integration, the VLSI Journal, 44(1), 22-38. Lien externe
Hasan, S. R., Bélanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(8), 2020-2031. Lien externe
Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10), 2696-707. Lien externe
Hasib, O. A.-T., Sawan, M., & Savaria, Y. (mai 2010). Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. Lien externe
Hasan, S. R., Pontikakis, B., & Savaria, Y. (mai 2009). An all-digital skew-adaptive clock scheduling algorithm for heterogeneous multiprocessor systems on chips (MPSoCs) [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan. Lien externe
Hashemi, S., Sawan, M., & Savaria, Y. (juin 2009). Fully-integrated low-voltage high-efficiency CMOS rectifier for wirelessly powered devices [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Hashemi, S., Sawan, M., & Savaria, Y. (décembre 2009). A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices [Communication écrite]. 16th IEEE International Conference on Electronics, Circuits and Systems, Yasmine Hammamet, Tunisia. Lien externe
Hashemi, S., Sawan, M., & Savaria, Y. (2009). A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results. Microelectronics Journal, 40(11), 1547-1554. Lien externe
Hasan, S. R., Bélanger, N., & Savaria, Y. (2008). All digital skew tolerant synchronous interfacing methods for high-Performance point-to-point communication in DSM SoCs. (Rapport technique n° EPM-RT-2008-10). Disponible
Hasan, S. R., Belanger, N., & Savaria, Y. (octobre 2008). All-digital skew-tolerant interfacing method for systems with rational frequency ratios among multiple clock domains: leveraging a priori timing information [Communication écrite]. 1st Microsystems and Nanoelectronics Research Conference. Lien externe
Hasan, S. R., & Savaria, Y. (mai 2007). Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, USA (4 pages). Lien externe
Hadjiat, K., St-Pierre, F., Bois, G., Savaria, Y., Langevin, M., & Paulin, P. (décembre 2007). An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept [Communication écrite]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco. Lien externe
Hasan, S. R., & Savaria, Y. (août 2007). Metastability tolerant mesochronous synchronization [Communication écrite]. 50th Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montreal, QC, Canada. Lien externe
Hashemi, S., Sawan, M., & Savaria, Y. (décembre 2007). A novel fully-integrated low-drop voltage cmos rectifier for wirelessly powered devices [Communication écrite]. IEEE International Conference on Microelectronics, Cairo, Egypt. Lien externe
Huang, Z., Savaria, Y., Sawan, M., & Meinga, R. (mai 2006). High-voltage operational amplifier based on dual floating-gate transistors [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. Lien externe
Hashemi, S., Sawan, M., & Savaria, Y. (mai 2006). A power planning model for implantable stimulators [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. Lien externe
Hashemi, S., Sawan, M., & Savaria, Y. (décembre 2005). Modeling power budget requirements of implantable electronic devices [Communication écrite]. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2005), Tunisie. Lien externe
Hashemi, S., Sawan, M., & Savaria, Y. (juin 2004). Characterization of Stress Induced Defects in Deep Sub-Micron MOSFETS [Communication écrite]. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Hasan, S. K., Landry, A., Savaria, Y., & Nekili, M. (juin 2004). Design constraints of hypertransport-compatible networks-on-chip [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, QC, Canada. Lien externe
Huang, Z., Savaria, Y., & Sawan, M. (juin 2004). Robust design of a dynamically controlled low-power level-up shifter operating up to 300V [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Hashemi, S., Sawan, M., & Savaria, Y. (janvier 2002). Analysis of power chains in transcutaneously powered electronic implants [Communication écrite]. 7th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 2002), Lubljana. Non disponible
Hébert, O., Kraljic, I. C., & Savaria, Y. (mai 2000). A method to derive application-specific embedded processing cores [Communication écrite]. 8th International Workshop on Hardware/Software Codesign (CODES 2000), San Diego, CA, USA. Lien externe
Hrytzak, R., Savaria, Y., & Goslin, G. (janvier 1997). Reconfigurable computing greatly simplifies system development [Communication écrite]. DSP World Spring Design Conference. Non disponible
Haccoun, D., & Savaria, Y. (1990). Étude et réalisation de codeurs et décodeurs à haute vitesse pour codes convolutionnels. (Rapport technique n° EPM-RT-90-08). Disponible
Haccoun, D., Lavoie, P., & Savaria, Y. (1987). New architectures for fast convolutional encoders and threshold decoders. (Rapport technique n° EPM-RT-87-46). Disponible
Ignat, N., Nicolescu, B., Savaria, Y., & Nicolescu, G. Soft-Error Classification and Impact Analysis on Real-Time Operating Systems [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2006). Lien externe
Izouggaghen, B., Khouas, A., & Savaria, Y. (mai 2004). Spurs modeling in direct digital period synthesizers related to phase accumulator truncation [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. Lien externe
Jin, Z.-F., Yang, M., Savaria, Y., & Wu, K. (juillet 2004). Analysis of gate modulation in nanoscale field effect transistors using an equivalent substrate integrated waveguide (SIW) model [Communication écrite]. 10th International Symposium on Antenna Technology and Applied Electromagnetics and URSI Conference (ANTEM/URSI 2004), Ottawa, Ont., Canada. Lien externe
Jiang, Y. T., Wang, Y. K., Song, X. Y., & Savaria, Y. (2004). Computation of Signal Output Probability for Boolean Functions Represented by Obdd. Computers & Mathematics With Applications, 47(12), 1865-1874. Lien externe
Jin, Z.-F., Laurin, J.-J., & Savaria, Y. Comparison of Propagation Characteristics Between Single and Coupled Mis Interconnect Topologies in Vlsi Circuits [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). Lien externe
Jin, Z.-F., Laurin, J.-J., & Savaria, Y. (2002). A practical approach to model long MIS interconnects in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(4), 494-507. Lien externe
Jiang, Y., Tang, Y., Wang, Y., & Savaria, Y. (mai 1999). Evaluating the ouptput probability of boolean functions without floating point operations [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1999), Edmonton, AB, Canada. Lien externe
Jin, Z.-F., Laurin, J.-J., & Savaria, Y. New approach to analyze interconnect delays in RC wire models [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999). Non disponible
Kern, J., Henwood, S., Mordido, G., Dupraz, E., Aissa-El-Bey, A., Savaria, Y., & Leduc-Primeau, F. (2024). Fast and Accurate Output Error Estimation for Memristor-Based Deep Neural Networks. IEEE Transactions on Signal Processing, 72, 1205-1218. Lien externe
Kaced, K., Genevey, S., Savaria, Y., & David, J. P. (juin 2024). A Flexible Thermal/Solar Energy Harvesting System with Hysteretic Control and Maximum Power Point Tracking Regulation for IoT Devices [Communication écrite]. 22nd IEEE Interregional NEWCAS Conference (NEWCAS 2024), Piscataway, NJ, USA. Lien externe
Kern, J., Henwood, S., Mordido, G., Dupraz, E., Aissa-El-Bey, A., Savaria, Y., & Leduc-Primeau, F. (juin 2022). MemSE: Fast MSE Prediction for Noisy Memristor-Based DNN Accelerators [Communication écrite]. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era, Incheon, South Korea. Lien externe
Kazma, G., Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (mai 2017). Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories [Communication écrite]. Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta. Lien externe
Kazma, G., Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (juin 2017). Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Khanzadi, H., Savaria, Y., & David, J. P. (juin 2017). A data driven CGRA Overlay Architecture with embedded processors [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Kazma, G., Bany Hamad, G., Mohamed, O. A., & Savaria, Y. (décembre 2016). Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis [Communication écrite]. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2016), Monte Carlo, Monaco. Lien externe
Khelifi, M., Massicotte, D., & Savaria, Y. (mai 2016). Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. Lien externe
Khanzadi, H., Savaria, Y., & David, J. P. (juin 2015). Mapping applications on two-level configurable hardware [Communication écrite]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec (8 pages). Lien externe
Khelifi, M., Massicotte, D., & Savaria, Y. (octobre 2015). Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems [Communication écrite]. 1st IEEE Nordic Circuits and Systems Conference (NORCAS 2015), Oslo, Norway (4 pages). Lien externe
Keklikian, T., Langlois, J. M. P., & Savaria, Y. (juin 2014). A Memory Transaction Model for Sparse Matrix-Vector Multiplications on GPUs [Communication écrite]. 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivières, Canada. Lien externe
Kowarzyk, G., Belanger, N., Haccoun, D., & Savaria, Y. (2014). Optimizing the parallel tree-search for finding shortest-span error-correcting CDO codes. IEEE Transactions on Parallel and Distributed Systems, 25(11), 2992-3001. Lien externe
Kowarzyk, G., Belanger, N., Haccoun, D., & Savaria, Y. (2013). Efficient parallel search algorithm for determining optimal R=1/2 systematic convolutional self-doubly orthogonal codes. IEEE Transactions on Communications, 61(3), 865-876. Lien externe
Kowarzyk, G., Belanger, N., Haccoun, D., & Savaria, Y. (2012). Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Transactions on Communications, 60(1), 3-8. Lien externe
Kowarzyk, G., Bélanger, N., & Savaria, Y. (décembre 2011). A GPGPU-based software implementation of the PBDI deinterlacing algorithm [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Kowarzyk, G., Savaria, Y., & Haccoun, D. (mai 2008). Searching for short-span convolutional doubly self-orthogonal codes: a parallel implicitly-exhaustive-search algorithm [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2008), Niagara Falls, Ontario. Lien externe
Khali, H., Savaria, Y., & Houle, J.-L. (2005). A system level implementation strategy and partitioning algorithm for applications based on lookup tables. International Journal of Computer and Electrical Engineering, 31(7), 485-502. Lien externe
Khali, H., & Savaria, Y. (décembre 2003). Hardware-software co design model for real-time 3D image computation using active laser range finders : a case study [Communication écrite]. 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2003), Sharjah, United Arab Emirates. Lien externe
Khali, H., Savaria, Y., Houle, J. L., Rioux, M., Beraldin, J. A., & Poussart, D. (2003). Improvement of Sensor Accuracy in the Case of a Variable Surface Reflectance Gradient for Active Laser Range Finders. IEEE Transactions on Instrumentation and Measurement, 52(6), 1799-1808. Lien externe
Khali, H., Savaria, Y., & Houle, J.-L. (juillet 1997). Computational limits of homogeneous acceleration using lookup tables [Communication écrite]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Non disponible
Kafrounni, M., Thibeault, C., & Savaria, Y. (octobre 1997). Cost model for VLSI/MCM systems [Communication écrite]. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Lien externe
Kermouche, R., Audet, D., & Savaria, Y. (1995). On the optimization of integrated hierarchical bus architectures to achieve efficient fault-tolerance. Journal of Microelectronic Systems Integration, 3(1), 47-63. Non disponible
Khali, H., Savaria, Y., Houle, J.-L., Beraldin, J. A., Blais, F., & Rioux, M. (septembre 1995). VLSI chip for 3-D camera calibration [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, Québec. Lien externe
Kermouche, R., & Savaria, Y. (octobre 1994). Defect and fault tolerant scan chains [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1994), Montréal, Québec. Lien externe
Kermouche, R., Savaria, Y., & Audet, D. (janvier 1994). Harvest model of an integrated hierarchical-bus architecture [Communication écrite]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA. Lien externe
Kroumba, S. M., Bois, G., & Savaria, Y. (août 1994). Synthesis approach for the generation of parallel architectures [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Luinaud, T., Langlois, J. M. P., & Savaria, Y. (2022). Symbolic analysis for data plane programs specialization. ACM Transactions on Architecture and Code Optimization, 20(1), 1-21. Lien externe
Luinaud, T., Santiago da Silva, J., Langlois, J. M. P., & Savaria, Y. (février 2021). Design Principles for Packet Deparsers on FPGAs [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) (7 pages). Disponible
Luinaud, T., Stimpfling, T., Santiago da Silva, J., Savaria, Y., & Langlois, J. M. P. (mai 2020). Bridging the gap: FPGAs as programmable switches [Communication écrite]. 21st IEEE International Conference on High Performance Switching and Routing (HPSR 2020) (7 pages). Lien externe
Laparra, G., Li, M., Zhu, G., & Savaria, Y. (2020). Desynchronized Model Predictive Control for Large Populations of Fans in Server Racks of Datacenters. IEEE Transactions on Smart Grid, 11(1), 411-419. Lien externe
Luinaud, T., Stimpfling, T., Santiago Da Silva, J., Savaria, Y., & Langlois, J. M. P. (février 2020). Unleashing the Power of FPGAs as Programmable Switches [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, CA, USA (1 page). Lien externe
Leonardon, M., Cassagne, A., Leroux, C., Jego, C., Hamelin, L.-P., & Savaria, Y. (2019). Fast and Flexible Software Polar List Decoders. Journal of Signal Processing Systems for Signal Image and Video Technology, 91(8), 937-952. Lien externe
Léonardon, M., Leroux, C., Binet, D., Langlois, J. M. P., Jégo, C., & Savaria, Y. (mai 2018). Custom low power processor for polar decoding [Communication écrite]. IEEE International Symposium on Circuits & Systems (ISCAS 2018), Florence, Italy. Lien externe
Laflamme-Mayer, N., Kowarzyk, G., Blaquiere, Y., Savaria, Y., & Sawan, M. (2018). A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(2), 304-315. Lien externe
Li, M., Chen, C., Zhu, G., & Savaria, Y. (août 2018). Local Queueing-Based Data-Driven Task Scheduling for Multicore Systems [Communication écrite]. 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada. Lien externe
Lepercq, É., Blaquière, Y., & Savaria, Y. (2018). A pattern-based routing algorithm for a novel electronic system prototyping platform. Integration, 62, 224-237. Lien externe
Leonardon, M., Leroux, C., Jaaskelainen, P., Jego, C., & Savaria, Y. (décembre 2018). Transport Triggered Polar Decoders [Communication écrite]. 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing (ISTC 2018), Hong Kong (5 pages). Lien externe
Li, M., Zhu, G., Savaria, Y., & Lauer, M. (2017). Reliability Enhancement of Redundancy Management in AFDX Networks. IEEE Transactions on Industrial Informatics, 13(5), 2118-2129. Disponible
Luinaud, T., Savaria, Y., & Langlois, J. M. P. (mai 2017). An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search [Communication écrite]. Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta. Lien externe
Luinaud, T., Savaria, Y., & Langlois, J. M. P. (février 2017). An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only) [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, California. Lien externe
Lakhssassi, A., Palenychka, R., Savaria, Y., Sayde, M., & Zaremba, M. (2016). Monitoring thermal stress in wafer-scale integrated circuits by the attentive vision method using an infrared camera. IEEE Transactions on Circuits and Systems for Video Technology, 26(2), 412-424. Lien externe
Laflamme-Mayer, N., Blaquiere, Y., Savaria, Y., & Sawan, M. (2014). A configurable multi-rail power and I/O pad applied to wafer-scale systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(11), 3135-3144. Lien externe
Li, M., Lauer, M., Zhu, G., & Savaria, Y. (2014). Determinism enhancement of AFDX networks via frame insertion and sub-virtual link aggregation. IEEE Transactions on Industrial Informatics, 10(3), 1684-1695. Lien externe
Lakhssassi, A., Palenychka, R., Sayde, M., Savaria, Y., Zaremba, M., & Kengne, E. (septembre 2013). A spatiotemporal attention operator for monitoring thermo-mechanical stress in wafer-scale integrated circuits using an infrared camera [Communication écrite]. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy. Lien externe
Lepercq, E., Valorege, O., Basile-Bellavance, Y., Laflamme-Mayer, N., Blaquière, Y., & Savaria, Y. (octobre 2009). An interconnection network for a novel reconfigurable circuit board [Communication écrite]. 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada. Lien externe
Lacourse, A., Ducharme, M., St-Jean, H., Gagnon, Y., Savaria, Y., & Meunier, M. (2009). Tunable semiconductor component provided with a current barrier. (Brevet no US7564078). Lien externe
Lepercq, E., Blaquiere, Y., Norman, R., & Savaria, Y. (mai 2009). Workflow for an electronic configurable prototyping system [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan. Lien externe
Lu, Z., El-Fouladi, J., Martel, S., & Savaria, Y. (juin 2008). A hybrid bacteria and microparticle detection platform on a CMOS chip: design, simulation and testing considerations [Communication écrite]. 14th IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW 2008) (7 pages). Lien externe
Lu, Z., El-Fouladi, J., Savaria, Y., & Martel, S. (octobre 2007). A hybrid bacteria and microparticle detection platform on a CMOS chip [Communication écrite]. 11th International Conference on Miniaturized Systems for Chemistry and Life Science, Paris, France. Non disponible
Ling, W., & Savaria, Y. (mars 2005). Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations [Communication écrite]. 6th International Symposium on Quality Electronic Design, San Jose, California. Lien externe
Landry, A., Savaria, Y., & Nekili, M. (juin 2005). Circuits techniques for a 2 GHz AMBA AHB Bus [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, QC, Canada. Lien externe
Landry, A., Nekili, M., & Savaria, Y. (mai 2005). A novel 2 GHz Mulit-layer AMBA high-Speed bus interconnect matrix for SoC platforms [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Landry, A., Savaria, Y., & Nekili, M. (décembre 2004). A beyond-1 GHz high-speed bus for SoC DSP platforms [Communication écrite]. 16th International Conference on Microelectronics (ICM 2004), Tunis, Tunisia. Lien externe
Layachi, M., Savaria, Y., & Rochefort, A. The Effect of Pi-Coupling on the Electronic Properties of 1,4-Dithiol Benzene Stacking [Communication écrite]. International Conference on Mems, Nano and Smart Systems (ICMENS 2004). Lien externe
Lafrance, L.-P., & Savaria, Y. (juillet 2004). A framework for implementing reusable digital signal processing modules [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (4 pages). Lien externe
Ling, W., & Savaria, Y. (juillet 2004). Variable-precision multiplier for equalizer with adaptive modulation [Communication écrite]. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japon. Lien externe
Loiseau, L., & Savaria, Y. (2003). Design reuse. Dans System-on-chip for real-time applications (Vol. 711, p. 29-82). Lien externe
Lu, M., Savaria, Y., Qiu, B., & Taillefer, J. (novembre 2003). IEEE 1149.1 based defect and fault tolerant scan chain for wafer scale integration [Communication écrite]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states. Lien externe
Lemire, J. F., Aboulhamid, E. M., Savaria, Y., Bois, G., & Baron, A. (février 2003). Implementing e assertion checkers from an SDL executable specifications [Communication écrite]. DVCON, San José, USA. Non disponible
Loiseau, L., & Savaria, Y. (juillet 2002). Methodologies and Strategies for Effective Design-Reuse [Communication écrite]. System-on-Chip for Real-Time Applications. Lien externe
Lamarche, P. H., & Savaria, Y. (janvier 2003). VHDL source code generator and analysis tool to design linear interpolars [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Lafrance, L.-P., Cantin, M.-A., Savaria, Y., Sung, S. H., & Lavoie, P. (mai 2002). Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. Lien externe
Loiseau, L., & Savaria, Y. (2002). Methodologies and Strategies for Effective Design Reuse. Canadian Journal of Electrical and Computer Engineering, 27(4), 165-169. Non disponible
Le Chapelain, B., Mechain, A., Savaria, Y., & Bois, G. (mai 1999). Development of a high performance TSPC library for implementation of large digital building blocks [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. Lien externe
Lavoie, P., Crespo, J. F., & Savaria, Y. (1999). Generalization, Discrimination, and Multiple Categorization Using Adaptive Resonance Theory. IEEE Transactions on Neural Networks, 10(4), 757-767. Lien externe
Lavoie, P., Crespo, J. F., & Savaria, Y. (juin 1997). Multiple categorization using fuzzy ART [Communication écrite]. IEEE International Conference on Neural Networks (ICNN 1997), Houston, TX, USA. Lien externe
Lejmi, S., Bois, G., & Savaria, Y. (janvier 1996). On the effects of retiming applied to self-checking sequential circuit [Communication écrite]. 2nd IEEE On-Line Testing Workshop, Biarritz. Non disponible
Lavoie, P., Crespo, J.-F., & Savaria, Y. (janvier 1996). On the stability of Fuzzy ART [Communication écrite]. 18th Biennal Symposium on Communications, Kingston. Non disponible
Lavoie, P., Haccoun, D., & Savaria, Y. (1994). Systolic architecture for fast stack sequential decoders. IEEE Transactions on Communications, 42(2/3/4, pt.), 324-335. Lien externe
Lavoie, P., Haccoun, D., & Savaria, Y. (1988). Spécification d'un décodeur séquentiel rapide utilisant une queue prioritaire systolique. (Rapport technique n° EPM-RT-88-11). Disponible
Mashreghi-Moghadam, P., Ould-Bachir, T., & Savaria, Y. (2024). PrismParser: a framework for implementing efficient P4-programmable packet parsers on FPGA. Future Internet, 16(9), 307 (19 pages). Disponible
Mafi, H., Ben-Hamida, N., Aouini, S., & Savaria, Y. (2024). Digital Compensation of Timing Skew Mismatches in Time-Interleaved ADCs by Source Separation. IEEE Transactions on Instrumentation and Measurement, 3376008 (11 pages). Lien externe
Mafi, H., Ben-Hamida, N., Aouini, S., & Savaria, Y. (juin 2024). Digital Compensation of Timing-Skew Mismatches in TI-ADCs by Modulation and Source Separation [Communication écrite]. 22nd IEEE Interregional NEWCAS Conference (NEWCAS 2024), Sherbrooke, QC, Canada. Lien externe
Mafi, H., Bensenouci, M. A., Aouini, S., Honarparvar, M., Ben-Hamida, N., & Savaria, Y. (mai 2024). Utilization of Noise-Shaping in Mixed-Signal Timing-Skew Mismatch Calibration of TI-ADCs [Communication écrite]. 2024 IEEE International Symposium on Circuits and Systems (ISCAS 2024), Singapore (5 pages). Lien externe
Mohammadi, H. M., Edrisi, M. H., & Savaria, Y. (2023). Enhanced Artificial Vision for Visually Impaired Using Visual Implants. IEEE Access, 11, 80020-80029. Disponible
Mashreghi-Moghadam, P., Ould-Bachir, T., & Savaria, Y. An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs [Communication écrite]. 2023 IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, CA, USA (5 pages). Lien externe
Mafi, H., Ali, M., Savaria, Y., Honarparvar, M., & Ben-Hamida, N. (juin 2023). Background Calibration of Time-Interleaved ADCs with Polyphase Filters [Communication écrite]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). Lien externe
Makhroute, E.-M., Elharti, M.-A., Brouillard, V., Savaria, Y., & Ould-Bachir, T. (décembre 2023). Implementing and Evaluating a P4-based Access Gateway Function on a Tofino Switch [Communication écrite]. 6th International Conference on Advanced Communication Technologies and Networking (CommNet 2023), Rabat, Morocco (7 pages). Lien externe
Mashreghi-Moghadam, P., Ould-Bachir, T., & Savaria, Y. (mai 2022). A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. Lien externe
Meng, L., Zhu, G., & Savaria, Y. (mai 2018). Delay bound analysis for heterogeneous multicore systems using network calculus [Communication écrite]. 13th IEEE Conference on Industrial Electronics and Applications (ICIEA 2018), Wuhan, China. Lien externe
Mohajertehrani, M., Savaria, Y., & Sawan, M. (2018). Harvesting energy from aviation data lines: implementation and experimental results. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(6), 2048-2057. Lien externe
Mohajertehrani, M., Shafique, U., Savaria, Y., & Sawan, M. (décembre 2015). Harvesting energy from data lines for avionics applications: power conversion chain architecture [Communication écrite]. 27th International Conference on Microelectronics (ICM 2015), Casablanca, Maroc. Lien externe
Mirzadeh, Z., Boland, J.-F., & Savaria, Y. (mai 2015). Modeling the faulty behaviour of digital designs using a feed forward neural network approach [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal. Lien externe
Mahvash Mohammadi, H., Savaria, Y., & Langlois, J. M. P. (2012). Enhanced motion compensated deinterlacing algorithm. IET Image Processing, 6(8), 1041-1048. Lien externe
Mbaye, M. M., Belanger, N., Savaria, Y., & Pierre, S. (2012). Loop Acceleration Exploration for ASIP Architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), 684-696. Lien externe
Mohammadi, H. M., Savaria, Y., & Langlois, J. M. P. (2011). Hybrid video deinterlacing algorithm exploiting reverse motion estimation. IET Image Processing, 5(7), 611-618. Lien externe
Marche, D., & Savaria, Y. (2010). Modeling R-2R segmented-ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(1), 31-43. Lien externe
Marche, D., Savaria, Y., & Gagnon, Y. (2009). An improved switch compensation technique for inverted R-2R Ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(6), 1115-1124. Lien externe
Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (2009). Performance characterization for the implementation of content addressable memories based on parallel hashing memories. Dans Transactions on High-Performance Embedded Architectures and Compilers. II (Vol. 5470, p. 307-325). Lien externe
Marche, D., Savaria, Y., & Gagnon, Y. (2008). Laser Fine-Tuneable Deep-Submicrometer Cmos 14-Bit Dac. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(8), 2157-2165. Lien externe
Mbaye, M., Belanger, N., Savaria, Y., & Pierre, S. (juillet 2008). Loop-oriented metrics for exploring an application-specific architecture design-space [Communication écrite]. International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2008). Lien externe
Mohammadi, H. M., Langlois, J. M. P., & Savaria, Y. (2007). A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Transactions on Consumer Electronics, 53(3), 1117-1124. Lien externe
Mbaye, M. M., Belanger, N., Savaria, Y., & Pierre, S. (2007). A Novel Application-Specific Instruction-Set Processor Design Approach for Video Processing Acceleration. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 47(3), 297-315. Lien externe
Meunier, M., Gagnon, Y., Lacourse, A., Ducharme, M., Rioux, S., & Savaria, Y. (mai 2007). Precision resistor laser trimming for analog microelectronics [Communication écrite]. Photonic Applications Systems Technologies Conference, Baltimore, Maryland, USA. Lien externe
Mbaye, M., Lebel, D., Belanger, N., Savaria, Y., & Pierre, S. (mai 2006). Design exploration with an application-specific instruction-set processor for ELA deinterlacing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. Lien externe
Mahvash, M. H., Savaria, Y., & Langlois, J. M. P. (juin 2006). Real-time ELA de-interlacing with the Xtensa reconfigurable processor [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Mohammadi, H. M., Langlois, J. M. P., & Savaria, Y. (décembre 2006). A threshold-based deinterlacing algorithm using motion compensation and directional interpolation [Communication écrite]. 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France. Lien externe
Morin, D., Savaria, Y., & Sawan, M. (juin 2005). A 200 MSPS 10-bit pipelined ADC using digital calibration [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec City, Que., Canada. Lien externe
Mbaye, M., Bélanger, N., Savaria, Y., & Pierre, S. (mai 2005). Application Specific Instruction-Set Processor Generation for Video Processing Based on Loop Optimization [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Marche, D., Savaria, Y., & Gagnon, Y. (mai 2005). A New Switch Compensation Technique for Inverted R-2r Ladder Dacs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (juin 2005). Parallel hashing memories : an alternative to content addressable memories [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, QC, Canada. Lien externe
Morin, D., Normandin, F., Grandmaison, M. E., Dang, H., Savaria, Y., & Sawan, M. (juillet 2004). An intellectual property module for auto-calibration of time-interleaved pipelined analog-to-digital converters [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. Lien externe
Mbaye, M. M., Tohio, B., Savaria, Y., & Pierre, S. Performance of a Firewire-Ethernet Protocols Conversion on an Arm7 Embedded Processor [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). Lien externe
Meunier, M., Gagnon, Y., Savaria, Y., & Lacourse, A. (mai 2002). Laser tuning silicon microdevices for analogue microelectronics [Communication écrite]. SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging (Opto Canada 2002), Ottawa, ON, Canada. Lien externe
Meunier, M., Gagnon, Y., Savaria, Y., Lacourse, A., & Cadotte, M. (juin 2001). A novel laser trimming technique for microelectronics [Communication écrite]. European Materials Research Society 2001-Symposium L "Photon-Induced Surface Processing", Strasbourg, France. Publié dans Applied Surface Science, 186(1-4). Lien externe
Meunier, M., Gagnon, Y., Savaria, Y., Lacourse, A., & Cadotte, M. A novel laser trimming technique for microelectronics [Communication écrite]. 6th Conference on Laser Applications in Microelectronic and Optoelectronic Manufacturing (LAMOM 2001). Lien externe
Monté-Genest, G., Antaki, B., Patenaude, S., Savaria, Y., Thibeault, C., & Trouborst, P. (avril 2001). Tools for the characterization of bipolar CML testability [Communication écrite]. 19th IEEE VLSI Test Symposium (VTS 2001), Marina Del Rey, CA, USA. Lien externe
Marriott, P., Kraljic, I., & Savaria, Y. (janvier 1998). Parallel ultra large scale engine SIMD architectures for real time digital signal processing applications [Communication écrite]. International Conference on Computer Design (ICCD 1998), Austin. Lien externe
Noghabaei, S. M., Radin, R. L., Savaria, Y., & Sawan, M. (2022). A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(1), 440-451. Lien externe
Noghabaei, S. M., Radin, R. L., Savaria, Y., & Sawan, M. (mai 2018). A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (4 pages). Lien externe
Nsame, P., Bois, G., & Savaria, Y. (mai 2015). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platforms [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal. Lien externe
Nsame, P., Bois, G., & Savaria, Y. (août 2014). Adaptive real-time DSP acceleration for SoC applications [Communication écrite]. 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX. Lien externe
Nsame, P., Bois, G., & Savaria, Y. (décembre 2014). A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT [Communication écrite]. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France. Lien externe
Nsame, P., Bois, G., & Savaria, Y. (mai 2014). Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications [Communication écrite]. IEEE 23rd North Atlantic Test Workshop (NATW 2014), Johnson City, NY, USA (4 pages). Lien externe
Nguyen, H. H., Guillemot, M., Savaria, Y., & Blaquiere, Y. (octobre 2012). A new approach for pin detection for an electronic system prototyping reconfigurable platform [Communication écrite]. 23rd IEEE International Symposium on Rapid System Prototyping (RSP 2012), Tampere, Finland. Lien externe
Nishi, R., Zhu, G., & Savaria, Y. (avril 2012). Optimal scheduling policy for AFDX end-systems with virtual links of identical bandwidth allocation gap size [Communication écrite]. 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2012), Montréal, Québec. Lien externe
Nourivand, A., Al-Khalili, A. J., & Savaria, Y. (2012). Postsilicon Tuning of Standby Supply Voltage in Srams to Reduce Yield Losses Due to Parametric Data-Retention Failures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(1), 29-41. Lien externe
Nourivand, A., Al-Khalili, A. J., & Savaria, Y. (2011). Analysis of resistive open defects in drowsy SRAM cells. Journal of Electronic Testing: Theory and Applications, 27(2), 203-213. Lien externe
Naderi, A., Sawan, M., & Savaria, Y. (2009). Undersampling delta-sigma modulators : theory, design and implementation. Lien externe
Naderi, A., Sawan, M., & Savaria, Y. (2009). A low-power 2 GHz data conversion using delta modulation for portable application. Integration, the VLSI Journal, 42(1), 68-76. Lien externe
Norman, R., Valorge, O., Blaquière, Y., Lepercq, É., Basile-Bellavance, Y., El-Alaoui, Y., Prytula, R., & Savaria, Y. (juin 2008). An active reconfigurable circuit board [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, QC, Canada. Lien externe
Nourivand, A., Al-Khalili, A. J., & Savaria, Y. (août 2008). Aggressive leakage reduction of SRAMs using error checking and correcting (ECC) techniques [Communication écrite]. 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2008), Knoxville, TN, United states. Lien externe
Norman, R., Lepercq, E., Blaquiere, Y., Valorge, O., Basile-Bellavance, Y., Prytula, R., & Savaria, Y. (juin 2008). An interconnection network for a novel reconfigurable circuit board [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Naderi, A., Sawan, M., & Savaria, Y. (2008). On the design of undersampling continuous-time bandpass delta - Sigma modulators for gigahertz frequency A/D conversion. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(11), 3488-3499. Lien externe
Naderi, A., Sawan, M., & Savaria, Y. (août 2007). A 1.8GHz CMOS continuous-time band-pass delta-sigma modulator for RF receivers [Communication écrite]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montréal, Québec. Lien externe
Nicolescu, B., Ignat, N., Savaria, Y., & Nicolescu, G. (2006). Analysis of real-time systems sensitivity to transient faults using MicroC kernel. IEEE Transactions on Nuclear Science, 53(4), 1902-1909. Lien externe
Naderi, A., Sawan, M., & Savaria, Y. (mai 2006). Design of an active-RC bandpass filter for a subsampling RF delta modulator [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2006), Ottawa, ON, Canada. Lien externe
Naderi, A., Sawan, M., & Savaria, Y. (mai 2006). A novel 2-GHz band-pass delta modulator dedicated to wireless receivers [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. Lien externe
Naderi, A. H., Sawan, M., & Savaria, Y. (juin 2005). A 1-mW 2-GHz Q-enhanced LC bandpass filter for low-power RF applications [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005). Lien externe
Nicolescu, B., Gorse, N., Savaria, Y., Aboulhamid, E. M., & Velazco, R. (2005). On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach. IEEE Transactions on Nuclear Science, 52(5), 1555-1561. Lien externe
Nicolescu, B., Ignat, N., Savaria, Y., & Nicolescu, G. (septembre 2005). Sensitivity of real-time operating systems to transient faults : A cause study for microC kernel [Communication écrite]. 8th European Conference on Radiation and its Effects on Components and Systems (RADECS 2005). Lien externe
Nsame, P., & Savaria, Y. (juillet 2004). A customizable embedded SoC platform architecture [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. Lien externe
Nsame, P., & Savaria, Y. (septembre 2004). Multi-processor SoC integration: a case study on BlueGene [Communication écrite]. IEEE International SOC Conference (SOCC 2004). Lien externe
Nicolescu, B., Savaria, Y., & Velazco, R. (juillet 2004). Performance evaluation and failure rate prediction for the soft implemented error detection technique [Communication écrite]. 10th IEEE International On-Line Testing Symposium, Funchal, Madeira Island, Portugal. Lien externe
Nicolescu, B., Savaria, Y., & Velazco, R. (2004). Software detection mechanisms providing full coverage against single bit-flip faults. IEEE Transactions on Nuclear Science, 51(6), 3510-3518. Lien externe
Nicolescu, B., Gorse, N., Savaria, Y., Aboulhamid, E. M., & Velazco, R. (septembre 2004). Validating a dynamic signature monitoring approach using the LTL model checking technique [Communication écrite]. Workshop on Radiation Effects on Components and Systems (RADECS 2004), Madrid, Espagne. Non disponible
Nicolescu, B., Perronnard, P., Velazco, R., & Savaria, Y. (novembre 2003). Efficiency of transient bit-flips detection by software means a complete study [Communication écrite]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Cambridge, MA, USA. Lien externe
Nicolescu, B., Savaria, Y., & Velazco, R. (novembre 2003). SIED: software implemented error detection [Communication écrite]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states. Lien externe
Nsame, P., & Savaria, Y. (juin 2003). System-level design closure [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Nekili, M., Savaria, Y., & Bois, G. (mai 2001). Minimizing process-induced skew using delay tuning [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie. Lien externe
Nsame, P., Grou-Szabo, R., & Savaria, Y. (janvier 2000). INTIME: a multi-tool specification environment for ensuring timing constraints integrity for SOC design [Communication écrite]. IP Based Design 2000, Grenoble, France. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. Lien externe
Nsame, P., & Savaria, Y. (janvier 1999). Virtualising on-chip bus interfaces for improved embedded processor system performance [Communication écrite]. IFIP International Workshop on IP Based Synthesis and System Design, Grenoble, France. Non disponible
Nekili, M., Savaria, Y., Bois, G., Bayoumi, M. A., & Jullien, G. (février 1998). Design of clock distribution networks in presence of process variations [Communication écrite]. 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA. Lien externe
Nekili, M., Bois, G., & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. Lien externe
Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Rapport technique n° EPM-RT-94-09). Accès restreint
Nekili, M., Savaria, Y., & Bois, G. (mai 1994). Fast low-power driver for long interconnections in VLSI systems [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, UK. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (août 1994). A variable-size parallel regenerator for long integrated interconnections [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Nekili, M., & Savaria, Y. (mai 1992). Optimal methods of driving interconnections in VLSI circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
Oukaira, A., Said, D., Touati, D. E., El-Zarif, N., Hassan, A., Savaria, Y., & Lakhssassi, A. (2024). Novel peak-source-scanning (NPSS) model for thermal control of systems-in-package (SiP). IEEE Access, 12, 14842-14853. Disponible
Oukaira, A., Savaria, Y., Boukadoum, M., & Lakhssassi, A. (mai 2024). Advanced Simulation and Design Methodology of Josephson Traveling-Wave Parametric Amplifiers (JTWPA) for Quantum Electronics Applications [Communication écrite]. 4th International Conference on Innovative Research in Applied Science, Engineering and Technology (IRASET 2024), Fez, Morocco (5 pages). Lien externe
Oukaira, A., Touati, D. E., Hassan, A., Ali, M., Savaria, Y., & Lakhssassi, A. (octobre 2022). FEM-based Thermal Profile Prediction for Thermal Management of System-on-Chips [Communication écrite]. 8th International Conference on Optimization and Applications (ICOA 2022), Genoa, Italy (4 pages). Lien externe
Oukaira, A., Hassan, A., Ali, M., Savaria, Y., & Lakhssassi, A. (2022). Towards real-time monitoring of thermal peaks in systems-on-chip (SoC). Sensors, 22(15), 5904 (12 pages). Lien externe
Oukaira, A., Touati, D. E., Hassan, A., Ali, M., Savaria, Y., & Lakhssassi, A. (août 2021). Thermo-mechanical Analysis and Fatigue Life Prediction for Integrated Circuits (ICs) [Communication écrite]. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2021), Lansing, MI, USA. Lien externe
Portas, F., Bois, G., & Savaria, Y. (juin 2024). CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign [Communication écrite]. 22nd IEEE Interregional NEWCAS Conference (NEWCAS 2024), Sherbrooke, QC, Canada. Lien externe
Posso, J., Bois, G., & Savaria, Y. (juin 2024). Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC [Communication écrite]. 22nd IEEE Interregional NEWCAS Conference (NEWCAS 2024), Sherbrooke, QC, Canada. Lien externe
Posso, J., Bois, G., & Savaria, Y. (mai 2022). Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. Lien externe
Pal, N., Kilaru, A., Savaria, Y., & Lakhssassi, A. (juin 2017). Hybrid features of tamura texture and shape-based image retrieval [Communication écrite]. 5th International Conference on Advanced Computing, Networking, and Informatics (ICACNI 2017), Goa, India. Lien externe
Pal, N., Kilaru, A., Savaria, Y., & Lakhssassi, A. (juillet 2018). Thermal image processing to Recognize and Quantify Pain in Human Body [Communication écrite]. International Conference on Smart Computing and Electronic Enterprise (ICSCEE 2018), Shah Alam, Malaysia (5 pages). Lien externe
Prieur, D., Granger, E., Savaria, Y., & Thibeault, C. (2016). Efficient identification of faces in video streams using low-power multi-core devices. Dans Handbook of pattern recognition and computer vision (5e éd.). Lien externe
Pons, J.-F., Brault, J.-J., & Savaria, Y. (2013). Modeling, design and implementation of a low-power FPGA based asynchronous wake-up receiver for wireless applications. Analog Integrated Circuits and Signal Processing, 77(2), 169-182. Disponible
Pons, J.-F., Brault, J.-J., & Savaria, Y. (juin 2012). An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks [Communication écrite]. 10th IEEE International New Circuits and Systems Conference (NEWCAS 2012), Montréal, Québec. Lien externe
Pons, J.-F., Brault, J.-J., & Savaria, Y. (août 2012). State-holding free NULL Convention Logic [Communication écrite]. 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012), Boise, ID, United states. Lien externe
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (juin 2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (mai 2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana. Lien externe
Pontikakis, B., Boyer, F.-R., Savaria, Y., & Bui, H. T. (août 2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation [Communication écrite]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). Lien externe
Pontikakis, B., Boyer, F.-R., & Savaria, Y. (mai 2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. Lien externe
Provost, G., Cantin, M. A., Sawan, M., Cardinal, C., Savaria, Y., & Haccoun, D. (mai 2005). Fast parameters optimization of an iterative decoder using a configurable hardware accelerator [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japon. Lien externe
Pontikakis, B., Boyer, F.-R., & Savaria, Y. (juillet 2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period [Communication écrite]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. Lien externe
Peterson, K., & Savaria, Y. (mai 2004). Assertion-based on-line verification and debug environment for complex hardware systems [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. Lien externe
Planque, F., Kraljic, I. C., & Savaria, Y. (septembre 2000). Mapping irregular algorithms in a custom computing image processing framework [Communication écrite]. 3rd Annual Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD 2000), Laurel, Maryland. Non disponible
Poiré, P., Cantin, M.-A., Daniel, H., Blaquière, Y., Savaria, Y., Pocek, K. L., & Arnold, J. M. (avril 1998). A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing [Communication écrite]. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA. Lien externe
Poiré, P., Savaria, Y., Daniel, H., Cantin, M. A., & Blaquière, Y. (novembre 1998). Hardware/software codesign of a Fuzzy ART neural clusterer : The benefits of configurable computing [Communication écrite]. 3rd Conference on Configurable Computing, Boston MA, USA. Lien externe
Pera, F., Savaria, Y., & Bois, G. (juin 1997). Time delay measurement methods for integrated transmission lines and high speed cells characterization [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong. Lien externe
Qavamy, Z., Ghavami, B., Nabavi, M., & Savaria, Y. (août 2021). Non-parametric Statistical Static Timing Analysis based on Improved Parallel Monte Carlo [Communication écrite]. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2021), Lansing, Michigan. Lien externe
Refaei, A., Genevey, S., Audet, Y., & Savaria, Y. (2024). High-Efficiency Wide Input Power Range Three-Phase Radio Frequency Energy Harvester for IoT Applications. IEEE Transactions on Microwave Theory and Techniques, 3456690 (9 pages). Lien externe
Robache, R., Boland, J.-F., Thibeault, C., & Savaria, Y. (juin 2013). A methodology for system-level fault injection based on gate-level faulty behavior [Communication écrite]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. Lien externe
Rioux, S., Lacourse, A., Ducharme, M., Gagnon, Y., Savaria, Y., & Meunier, M. (mai 2005). Design methods for CMOS low-current finely tunable voltage references covering a wide output range [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Japon. Lien externe
Robert, M., Savaria, Y., & Wang, C. (juin 2004). Analysis of metrics used to compare analog-to-digital converters [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Richard, J.-F., & Savaria, Y. (juin 2004). High voltage charge pump using standard CMOS technology [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Regimbal, S., Savaria, Y., & Bois, G. (juillet 2004). Verification strategy determination using dependence analysis of transaction-level models [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. Lien externe
Regimbal, S., Lemire, J. F., Savaria, Y., Bois, G., Aboulhamid, M., & Baron, A. (juillet 2002). Aspect Partitioning for Hardware Verification Reuse [Communication écrite]. System-on-Chip for Real-Time Applications. Lien externe
Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E. M., & Baron, A. (juin 2003). Automating functional coverage analysis based on an executable specification [Communication écrite]. 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications. Lien externe
Renaud, M., & Savaria, Y. (mai 2003). A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2003). Lien externe
Richard, J. F., Lessard, B., Meingan, R., Martel, S., & Savaria, Y. (janvier 2003). High voltage interfaces for CMOS/DMOS technologies [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Renaud, M., & Savaria, Y. (mai 2002). A linear phase detector for arbitrary clock signals [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. Lien externe
Rzeszut, J., Kaminska, B., & Savaria, Y. (novembre 1995). New method for testing mixed analog and digital circuits [Communication écrite]. 4th Asian Test Symposium, Bangalore, India. Lien externe
Su, M., David, J. P., Savaria, Y., Pontikakis, B., & Luinaud, T. (mai 2022). An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. Lien externe
Salehi, M., Ali, M., Savaria, Y., & Sawan, M. (novembre 2020). A 58 nW 35 ppm/C oscillator for iot battery-less sensor applications [Communication écrite]. 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2020), Glasgow, UK (4 pages). Lien externe
Samadani, S. M., Savaria, Y., & Nerguizian, C. (mai 2020). Indoor localization using channel state information with regression artificial neural networks [Communication écrite]. 91st IEEE Vehicular Technology Conference (VTC 2020), Antwerp, Belgium (4 pages). Lien externe
Saeidi, R., Nabavi, M., & Savaria, Y. (août 2020). SRAM Security and Vulnerability to Hardware Trojan: Design Considerations [Communication écrite]. 63rd IEEE International Midwest Symposium on Circuits and Systems, (MWSCAS 2020), Springfield, MA, USA. Lien externe
Stimpfling, T., Belanger, N., Langlois, J. M. P., & Savaria, Y. (2019). SHIP: a scalable high-performance IPv6 lookup algorithm that exploits prefix characteristics. IEEE/ACM Transactions on Networking, 27(4), 1529-1542. Lien externe
Stimpfling, T., Langlois, J. M. P., Bélanger, N., & Savaria, Y. (mai 2018). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis [Communication écrite]. 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.. Lien externe
Stimpfling, T., Bélanger, N., Cherkaoui, O., Béliveau, A., Béliveau, L., & Savaria, Y. (2017). Extensions to decision-tree based packet classification algorithms to address new classification paradigms. Computer Networks, 122, 83-95. Lien externe
Siaka, F., Akbarniai Tehrani, M., Laurin, J.-J., & Savaria, Y. (2017). Radar system with enhanced angular resolution based on a novel frequency scanning reflector antenna. IET Radar, Sonar & Navigation, 11(2), 350-358. Lien externe
Sarbishei, I., Vakili, S., Langlois, J. M. P., & Savaria, Y. (mai 2017). Scalable memory-less architecture for string matching with FPGAs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD. Lien externe
Sion, G., Blaquiere, Y., & Savaria, Y. (juillet 2015). Defect diagnosis algorithms for a field programmable interconnect network embedded in a very large area integrated circuit [Communication écrite]. 21st International On-Line Testing Symposium (IOLTS 2015), Athena Pallas, Greece. Lien externe
Shaheen, M. A., Hamoui, A. A., & Savaria, Y. (juin 2014). A current-output DAC for low-power low-noise log-domain modulators [Communication écrite]. 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivieres, QC, Canada. Lien externe
Shaheen, M. A., Savaria, Y., & Hamoui, A. A. (2014). Design and modeling of high-resolution multibit log-domain modulators. Analog Integrated Circuits and Signal Processing, 79(3), 569-582. Lien externe
Stimpfling, T., Savaria, Y., Beliveau, A., Belanger, N., & Cherkaoui, O. (juin 2013). Optimal packet classification applicable to the OpenFlow context [Communication écrite]. 1st ACM Workshop on High Performance and Programmable Networking (HPPN 2013), New York, NY, United states. Lien externe
Singh, R., Audet, Y., Gagnon, Y., Savaria, Y., Boulais, E., & Meunier, M. (2011). A laser-trimmed rail-to-rail precision CMOS operational amplifier. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), 75-79. Lien externe
Sahraii, N., Savaria, Y., Thibeault, C., & Gagnon, F. (juin 2008). Scheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Salomon, M.-É., Izouggaghen, B., Khouas, A., & Savaria, Y. (2008). Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. IEEE Transactions on Instrumentation and Measurement, 57(10), 2320-2328. Lien externe
Singh, R., Audet, Y., Gagnon, Y., & Savaria, Y. (mai 2007). Integrated circuit trimming technique for offset reduction in a precision CMOS amplifier [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, USA. Lien externe
Saheb, J.-F., Richard, J.-F., Sawan, M., Meingan, R., & Savaria, Y. (2007). System integration of high voltage electrostatic MEMS actuators. Analog Integrated Circuits and Signal Processing, 53(1), 27-34. Lien externe
Sawan, M., Harvey, J.-F., Roy, M., Coulombe, J., Savaria, Y., & Donfack, C. (2006). Body electronic implant and artificial vision system thereof. (Brevet no US7027874). Lien externe
Salomon, M. E., Khouas, A., & Savaria, Y. (mai 2005). A Complete Spurs Distribution Model for Direct Digital Period Synthesizers [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Sawan, M., Djemouai, A., El-Sankary, K., Dang, H., Naderi, A., Savaria, Y., & Gagnon, F. (juin 2005). High speed ADCs dedicated for wideband wireless receivers [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, QC, Canada. Lien externe
Saheb, J. F., Richard, J.-F., Meingan, R., Sawan, M., & Savaria, Y. (juin 2005). System integration of high voltage electrostatic MEMS Actuators [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, Canada. Lien externe
Savaria, Y., El Hassan, F., Khali, H., & Sawan, M. (janvier 1998). Effective hardware/software implementation of a viterbi decoder using an FPGA-based reconfigurable computing platform [Communication écrite]. FDP 1998. Non disponible
Savaria, Y. (1998). Study of neural networks for clustering radar signals: Final report. (Rapport technique n° 98-610). Non disponible
Savaria, Y., Bois, G., Popovic, P., & Wayne, A. Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems [Communication écrite]. High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic. Lien externe
St-Amand, R., Sawan, M., & Savaria, Y. (1996). Design and optimization of a low DC offset CMOS current-source dedicated to implantable miniaturized stimulators. Analog Integrated Circuits and Signal Processing, 11(1), 47-61. Lien externe
Soufi, M., Rochon, S., Savaria, Y., & Kaminska, B. (avril 1996). Design and performance of CMOS TSPC cells for high speed pseudo random testing [Communication écrite]. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe
Savaria, Y., Thibeault, C., & Ivanov, A. (1996). IEEE VSLI test symposium - meeting the quality challenge. IEEE Design & Test of Computers, 13(3), 110-112. Non disponible
Sawan, M., St-Amand, R., & Savaria, Y. (décembre 1995). Design and optimization of programmable biphasic current-sources [Communication écrite]. 2nd annual International Conference on Electronics, Circuits and Systems (ICECS 1995), Amman, Jordan. Non disponible
Soufi, M., Savaria, Y., & Kaminska, B. (avril 1995). On the design of at-speed testable VLSI circuits [Communication écrite]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe
Soufi, M., Savaria, Y., & Kaminska, B. (avril 1995). On Using partial reset for pseudo-random testing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA. Lien externe
Soufi, M., Savaria, Y., Darlay, F., & Kaminska, B. (1995). Producing reliable initialization and test of sequential circuits with pseudorandom vectors. IEEE Transactions on Computers, 44(10), 1251-1256. Lien externe
St-Amand, R., Savaria, Y., & Sawan, M. (août 1994). Design optimization of a current source for microstimulator applications [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Savaria, Y., Chtchvyrkov, D., & Currie, J. F. (mai 1994). Fast CMOS voltage-controlled ring oscillator [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
St.-Amand, R., Sawan, M., & Savaria, Y. (novembre 1994). Generation of balanced bipolar stimuli based on current sources without coupling capacitor [Communication écrite]. 16th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 1994), Baltimore, MD, USA. Lien externe
Savaria, Y. (1994). Parallel microprocessor architecture. (Brevet no US5276893). Lien externe
Soufi, M., Savaria, Y., Kaminska, B., & Darlay, F. (1994). Producing reliable initialization and test of sequential circuits with pseudo-random vectors. (Rapport technique n° EPM-RT-94-23). Accès restreint
Savaria, Y. (1988). Conception et vérification des circuits VLSI. Non disponible
Touati, D. E., Oukaira, A., Hassan, A., Ali, M., Savaria, Y., & Lakhssassi, A. (2024). Thermal analysis of system in package considering boundary conditions for long-term reliability studies. IEEE Access, 12, 3396373 (12 pages). Disponible
Touati, D. E., Oukaira, A., Hassan, A., Ali, M., Lakhssassi, A., & Savaria, Y. (2023). Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors. Electronics, 12(13), 18 pages. Disponible
Taghizadeh, R. G., Marvasti, M. B., Asghari, S. A., Taghizadeh, R. G., Nabavi, M., & Savaria, Y. (2021). IBU: An In-block Update Address Mapping Scheme for Solid-state Drives. IEEE Access, 10, 4934-4947. Lien externe
Trigui, A., Ali, M., Hached, S., David, J. P., Ammari, A. C., Savaria, Y., & Sawan, M. (2020). Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(11), 3978-3990. Lien externe
Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (2019). Energy Efficient Generic Demodulator for High Data Transmission Rate Over an Inductive Link for Implantable Devices. IEEE Access, 7, 159379-159389. Lien externe
Trigui, A., Hached, S., Ammari, A., Savaria, Y., & Sawan, M. (2019). Maximizing Data Transmission Rate for Implantable Devices Over a Single Inductive Link: Methodological Review. IEEE Reviews in Biomedical Engineering, 12, 72-87. Lien externe
Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (2018). A 1.5-pJ/bit, 9.04-Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(10), 1420-1424. Lien externe
Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (juin 2017). A 14.5 W generic carrier width demodulator for telemetry-based medical devices [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Tazi, F. Z., Thibeault, C., & Savaria, Y. (mai 2016). Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA [Communication écrite]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2016), Vancouver, British Columbia (5 pages). Lien externe
Tehrani, M. A., Savaria, Y., & Laurin, J.-J. (2016). Multiple targets direction-of-arrival estimation in frequency scanning array antennas. IET Radar, Sonar and Navigation, 10(3), 624-631. Lien externe
Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (juin 2016). Quad-Level Carrier Width Modulation demodulator for micro-implants [Communication écrite]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Lien externe
Tazi, F. Z., Thibeault, C., Savaria, Y., Pichette, S., & Audet, Y. (2014). On extra delays affecting I/O blocks of an SRAM-based FPGA due to ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3138-3145. Lien externe
Trabelsi, A., & Savaria, Y. (juin 2013). A 2D Gaussian smoothing kernel mapped to heterogeneous platforms [Communication écrite]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. Lien externe
Tehrani, M. A., Laurin, J.-J., & Savaria, Y. (avril 2013). Angular superresolution algorithm for frequency scanning array antennas [Communication écrite]. IEEE Radar Conference (RadarCon 2013), Ottawa, ON, Canada. Lien externe
Tremblay, J.-P., Savaria, Y., Zhu, G., Thibeault, C., & Bouanen, S. (octobre 2013). A hardware prototype for integration, test and validation of avionic networks [Communication écrite]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. Lien externe
Thibeault, C., Hariri, Y., Hasan, S. R., Hobeika, C., Savaria, Y., Audet, Y., & Tazi, F. Z. (2013). A library-based early soft error sensitivity analysis technique for SRAM-based FPGA design. Journal of Electronic Testing: Theory and Applications, 29(4), 457-471. Lien externe
Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2012). Real-time dual-microphone speech enhancement. Dans Ramakrishnan, S. (édit.), Speech Enhancement, Modeling and Recognition - Algorithms and Applications (p. 19-34). Disponible
Trentin, D., Savaria, Y., Zhu, G., & Thibeault, C. (octobre 2012). An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization [Communication écrite]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ. Publié dans SAE International Journal of Aerospace, 5(1). Lien externe
Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquière, Y., Moupfouma, F., & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65. Lien externe
Tremblay, J.-P., Savaria, Y., Zhu, G., Thibeault, C., & Bouanen, S. (octobre 2012). A System Architecture for Smart Sensors Integration in Avionics Applications [Communication écrite]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ. Publié dans SAE International Journal of Aerospace, 5(1). Lien externe
Tawk, M., Zhu, G., Liu, X., Jian, L., Savaria, Y., & Hu, F. (octobre 2011). Optimal scheduling and delay analysis for AFDX end-systems [Communication écrite]. SAE AeroTech Congress and Exhibition (AEROTECH 2011), Toulouse, France. Lien externe
Tawk, M., Zhu, G., Savaria, Y., Liu, X., Li, J., & Hu, F. (octobre 2011). A tight end-to-end delay bound and scheduling optimization of an avionics AFDX network [Communication écrite]. 30th Digital Avionics Systems Conference (DASC 2011), Seattle, WA, United states. Lien externe
Tanguay, L.-F., Savaria, Y., & Sawan, M. (juin 2010). A 640 µW frequency synthesizer dedicated to implantable medical microsystems in 90-nm CMOS [Communication écrite]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. Lien externe
Tanguay, L.-F., Sawan, M., & Savaria, Y. (2009). A very-high output impedance charge pump for low-voltage low-power PLLs. Microelectronics Journal, 40(6), 1026-1031. Lien externe
Tremblay, J.-P., Savaria, Y., Thibeault, C., & Mbaye, M. (octobre 2008). Improving resource utilization in an multiple asynchronous ALU DSP architecture [Communication écrite]. 1st Microsystems and Nanoelectronics Research Conference. Lien externe
Tanguay, L.-F., Sawan, M., & Savaria, Y. (novembre 2008). A very-high output impedance current mirror for very-low voltage biomedical analog circuits [Communication écrite]. IEEE Asia-Pacific Conference on Circuits and Systems, Macao, China. Lien externe
Trabelsi, A., Boyer, F.-R., Savaria, Y., & Boukadoum, M. (août 2007). Improving LPC Analysis of Speech in Additive Noise [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. Lien externe
Trabelsi, A., Boyer, F.-R., Savaria, Y., & Boukadoum, M. (décembre 2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis [Communication écrite]. 14h IEEE International Conference on Electronics, Circuits & Systems, Marrakech, Morocco. Lien externe
Trabelsi, A., Boyer, F.-R., & Savaria, Y. (août 2007). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise [Communication écrite]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). Lien externe
Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise. (Rapport technique n° EPM-RT-2006-09). Disponible
Tanguay, B., Savaria, Y., & Sawan, M. (décembre 2004). Accelerating equalization algorithms using the Xtensa configurable processor [Communication écrite]. 16th International Conference on Microelectronics (ICM 2004), Tunisie. Lien externe
Tohio, B., Pierre, S., Savaria, Y., & Mbaye, M. M. (mai 2004). Protocol convertibility in network processing environments [Communication écrite]. 6th WSEAS International Conference on Telecommunications and Informatics (TELE-INFO 2004), Cancun, Mexico. Publié dans WSEAS Transactions on Communications, 3(1). Non disponible
Trabelsi, A., Savaria, Y., & Audet, Y. (janvier 2003). Automatic offset correction technique based on active load tuning [Communication écrite]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Non disponible
Tang, Y., Qian, L., Wang, Y., & Savaria, Y. (mai 2003). New memory reference reduction method for FFT implementation on DSP [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand. Lien externe
Tohio, B., Pierre, S., Savaria, Y., & Mbaye, M. M. (mai 2003). Protocol Convertibility in a Network Processing Environment [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), Montréal, Québec. Lien externe
Thériault, L., Audet, D., & Savaria, Y. (mai 2001). Performance estimators for hardware/software co-design [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1995). Equivalence proofs of some yield modeling methods for defect-tolerant integrated-circuits. IEEE Transactions on Computers, 44(5), 724-728. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1994). A fast method to evaluate the optimum number of spares in defect-tolerant integrated-circuits. IEEE Transactions on Computers, 43(6), 687-697. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1992). Test quality of hierarchical defect-tolerant integrated circuits. Journal of Electronic Testing, 3(1), 93-102. Lien externe
Thibeault, C., & Savaria, Y. (novembre 1992). Comparing results from defect-tolerant yield models [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1992), Dallas, TX, United states. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1990). Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits. (Rapport technique n° EPM-RT-90-11). Accès restreint
Thibeault, C., Savaria, Y., & Houle, J.-L. (1988). Yield formula for two-level hierarchical fault-tolerant integrated circuit. (Rapport technique n° EPM-RT-88-25). Accès restreint
Vakili, S., Langlois, J. M. P., Savaria, Y., & Manjikian, N. (2018). Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Communications, 12(7), 868-875. Lien externe
Vakili, S., Langlois, J. M. P., Boughzala, B., & Savaria, Y. (mars 2016). Memory-efficient string matching for intrusion detection systems using a high-precision pattern grouping algorithm [Communication écrite]. 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California. Lien externe
Vakili, S., Gil, D. C., Langlois, J. M. P., Savaria, Y., & Bois, G. (décembre 2011). Customized embedded processor design for global photographic tone mapping [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Valorge, O., André, W., Savaria, Y., & Blaquière, Y. (juin 2011). Power supply analysis of a large area integrated circuit [Communication écrite]. 9th IEEE International New Circuits and Systems Conference (NEWCAS 2011), Bordeaux, France. Lien externe
Valorge, O., Blaquiere, Y., & Savaria, Y. (décembre 2010). A spatially reconfigurable fast differential interface for a wafer scale configurable platform [Communication écrite]. 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010), Athens, Greece. Lien externe
Valorge, O., Nguyen, A. T., Blaquière, Y., Norman, R., & Savaria, Y. (août 2008). Digital signal propagation on a wafer-scale smart active programmable interconnect [Communication écrite]. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), St. Julian's, Malta. Lien externe
Valorge, O., Marche, D., Lacourse, A., Sawan, M., & Savaria, Y. (décembre 2007). Signal Integrity Analysis of a High Precision D/A Converter [Communication écrite]. 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco. Lien externe
Vado, P., Savaria, Y., Zoccarato, Y., & Robach, C. (mai 2000). A methodology for validating digital circuits with mutation testing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland. Lien externe
Vinh, H. T., Audet, D., & Savaria, Y. (septembre 1993). Performance models for optimizing a hierarchical-bus multiprocessor architecture [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1993), Vancouver, BC, Canada. Lien externe
Wu, Y., Ding, Y., Ding, S., Savaria, Y., & Li, M. (2021). Autonomous Last-Mile Delivery Based on the Cooperation of Multiple Heterogeneous Unmanned Ground Vehicles. Mathematical Problems in Engineering, 2021, 1-15. Lien externe
Wang, J., Zeng, Y., Wei, S., Wei, Z., Wu, Q., & Savaria, Y. (2021). Multi-Sensor Track-to-Track Association and Spatial Registration Algorithm under Incomplete Measurements. IEEE Transactions on Signal Processing, 69, 3337-3350. Lien externe
Wu, Y., Li, M., Li, G., & Savaria, Y. (2021). Persistence region monitor with a pheromone-inspired robot swarm sensor network. IEEE Internet of Things Journal, 9(14), 12093-12110. Lien externe
Wolff, B., Fradj, B., Belanger, N., & Savaria, Y. (août 2018). Extending a CPU Cache for Efficient IPv6 Lookup [Communication écrite]. 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada. Lien externe
Wild, G., Savaria, Y., & Meunier, M. (mai 2005). Characterization of Laser-Induced Photoexcitation Effect on a Surrounding CMOS Ring Oscillator [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Yang, K., Li, M., Zhu, G., & Savaria, Y. (2017). A DAQM-Based Load Balancing Scheme for High Performance Computing Platforms. IEEE Access, 5, 22504-22513. Disponible
Zhang, Y., Savaria, Y., Sawan, M., & Leduc-Primeau, F. (juin 2024). S³ 1DCNN: A Compact Stacked Spectral-Spatial Attention 1DCNN for Seizure Prediction with Wearables [Communication écrite]. 22nd IEEE Interregional NEWCAS Conference (NEWCAS 2024), Sherbrooke, QC, Canada. Lien externe
Zeng, Y., Wang, J., Wei, S., Sun, J., Lei, P., Savaria, Y., & Zhang, C. (2024). Spatial Registration of Heterogeneous Sensors on Mobile Platforms. IEEE Transactions on Signal Processing, 72, 1839-1853. Lien externe
Zhang, Y., Savaria, Y., Zhao, S., Mordido, G., Sawan, M., & Leduc-Primeau, F. (juillet 2022). Tiny CNN for Seizure Prediction in Wearable Biomedical Devices [Communication écrite]. 44th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2022), Glasgow, United Kingdom. Lien externe
Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (2015). Design intelligence for interconnection realization in power-managed SoCs. Dans Computational Intelligence in Digital and Network Designs and Applications (p. 69-96). Lien externe
Zarrabi, H., Al-Khalili, A., & Savaria, Y. (décembre 2014). Vt-conscious repeater insertion in power-managed VLSI [Communication écrite]. International Symposium on Integrated Circuits (ISIC 2014), Singapore. Lien externe
Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (décembre 2011). Activity management in battery-powered embedded systems: A case study of ZigBee® WSN [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Zarrabi, H., Al-Khalili, A., & Savaria, Y. (mai 2011). Repeater insertion in power-managed VLSI systems [Communication écrite]. 21st Great Lakes Symposium on VLSI (GLSVLSI 2011), Lausanne, Switzerland. Lien externe
Zarrabi, H., Zilic, Z., Savaria, Y., & Al-Khalili, J. A. (2010). On the Efficient Design & Synthesis of Differential Clock Distribution Networks. Dans Wang, Z. (édit.), VLSI (p. 331-352). Disponible
Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (mai 2010). An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. Lien externe
Zarreabi, H., Al-Khalili, A. J., & Savaria, Y. (décembre 2009). Estimation of energy performance in computing platforms [Communication écrite]. 16th IEEE International Conference on Electronics, Circuits and Systems, Yasmine Hammamet, Tunisia. Lien externe
Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (mai 2009). An interconnect-aware delay model for dynamic voltage scaling in nm technologies [Communication écrite]. 19th ACM Great Lakes Symposium on VLSI, Boston, MA, United states. Lien externe
Zarrabi, H., Zilic, Z., Al-Khalili, A. J., & Savaria, Y. (août 2007). A methodology for parallel synthesis of zero skew differential clock distribution networks [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montreal, QC, Canada. Lien externe
Zhengrong, H., Savaria, Y., & Sawan, M. (juillet 2004). A dynamically controlled and refreshed low-power level-up shifter [Communication écrite]. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japon. Lien externe
