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Items where Author is "Savaria, Yvon"

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Number of items: 22.


Audet, D., Chouinard, G., Cyr, C., Houle, J.-L., & Savaria, Y. (1988). IMAGE2 : un circuit multiprocesseur pour le traitement parallèle. (Technical Report n° EPM-RT-88-35). Restricted access

Audet, D., Savaria, Y., & Houle, J.-L. (1988). Performance improvements of VLSI parallel systems, using dynamic concatenation of processing resources. (Technical Report n° EPM-RT-88-36). Restricted access


Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). HPQS: A fast, high-capacity, hybrid priority queuing system for high-speed networking devices. IEEE Access, 7, 130672-130684. Available

Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). A high-speed, scalable, and programmable traffic manager architecture for flow-based networking. IEEE Access, 7, 2231-2243. Available


Currie, J. F., Savaria, Y., & Dionne, J.-P. (1988). Réalisation d'un diviseur de fréquence numérique sur AsGa. (Technical Report n° EPM-RT-88-03). Restricted access


Fiorentino, M., Thibeault, C., & Savaria, Y. (2021). Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow. IET Computers & Digital Techniques, 15(6), 409-426. Available


Granger, É., Savaria, Y., & Lavoie, P. (2002). A pattern reordering approach based on ambiguity detection for on-line category learning. (Technical Report n° EPM-RT-2001-02). Available


Hassan, A., Ali, M., Trigui, A., Savaria, Y., & Sawan, M. (2019). A GaN-based wireless monitoring system for high-temperature applications. Sensors, 19(8), 1785 (17 pages). Available

Hasan, S. R., Bélanger, N., & Savaria, Y. (2008). All digital skew tolerant synchronous interfacing methods for high-Performance point-to-point communication in DSM SoCs. (Technical Report n° EPM-RT-2008-10). Available

Haccoun, D., & Savaria, Y. (1990). Étude et réalisation de codeurs et décodeurs à haute vitesse pour codes convolutionnels. (Technical Report n° EPM-RT-90-08). Available

Haccoun, D., Lavoie, P., & Savaria, Y. (1987). New architectures for fast convolutional encoders and threshold decoders. (Technical Report n° EPM-RT-87-46). Available


Luinaud, T., Santiago da Silva, J., Langlois, J. M. P., & Savaria, Y. (2021, February). Design Principles for Packet Deparsers on FPGAs [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) (7 pages). Available

Li, M., Zhu, G., Savaria, Y., & Lauer, M. (2017). Reliability Enhancement of Redundancy Management in AFDX Networks. IEEE Transactions on Industrial Informatics, 13(5), 2118-2129. Available

Lavoie, P., Haccoun, D., & Savaria, Y. (1988). Spécification d'un décodeur séquentiel rapide utilisant une queue prioritaire systolique. (Technical Report n° EPM-RT-88-11). Available


Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Technical Report n° EPM-RT-94-09). Restricted access


Pons, J.-F., Brault, J.-J., & Savaria, Y. (2013). Modeling, design and implementation of a low-power FPGA based asynchronous wake-up receiver for wireless applications. Analog Integrated Circuits and Signal Processing, 77(2), 169-182. Available


Soufi, M., Savaria, Y., Kaminska, B., & Darlay, F. (1994). Producing reliable initialization and test of seauential circuits with pseudo-random vectors. (Technical Report n° EPM-RT-94-23). Restricted access


Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2012). Real-time dual-microphone speech enhancement. In Ramakrishnan, S. (ed.), Speech Enhancement, Modeling and Recognition - Algorithms and Applications (19-34). Available

Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise. (Technical Report n° EPM-RT-2006-09). Available

Thibeault, C., Savaria, Y., & Houle, J.-L. (1990). Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits. (Technical Report n° EPM-RT-90-11). Restricted access

Thibeault, C., Savaria, Y., & Houle, J.-L. (1988). Yield formula for two-level hierarchical fault-tolerant integrated circuit. (Technical Report n° EPM-RT-88-25). Restricted access


Yang, K., Li, M., Zhu, G., & Savaria, Y. (2017). A DAQM-Based Load Balancing Scheme for High Performance Computing Platforms. IEEE Access, 5, 22504-22513. Available

List generated on: Sun Feb 5 02:11:32 2023 EST