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Items where Author is "Savaria, Yvon"

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Number of items: 640.

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Alizadeh, R., Savaria, Y., & Nerguizian, C. (2024). Characterization and Selection of WiFi Channel State Information Features for Human Activity Detection in a Smart Public Transportation System. IEEE Open Journal of Intelligent Transportation Systems, 5, 55-69. External link

Abuelnasr, A., Amer, M., Ali, M., Hassan, A., Gosselin, B., Ragab, A. R. A., & Savaria, Y. (2023). Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(4), 1555-1565. Available

Askarihemmat, M., Wagner, S., Bilaniuk, O., Hariri, Y., Savaria, Y., & David, J. P. (2023, January). BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU [Paper]. 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023), Tokyo, Japan. External link

Amer, M., Abuelnasr, A., Hassan, A., Ragab, A., Sawan, M., & Savaria, Y. (2023). A Half-bridge Gate Driver with Self-adjusting and Tunable Dead-time Modes for Efficient Switched-mode Power Systems. IEEE Transactions on Power Electronics, 15 pages. External link

Assaf, H., Savaria, Y., Ali, M., Nabavi, M., & Sawan, M. (2023). A Memristive Cell with Long Retention Time in 65 nm CMOS Technology. Advanced Electronic Materials, 9(6), 13 pages. External link

AskariHemmat, M.H., Dupuis, T., Fournier, Y., El Zarif, N., Cavalcante, M., Perotti, M., Gurkaynak, F., Benini, L., Leduc-Primeau, F., Savaria, Y., & David, J. P. Quark: an integer RISC-V vector processor for sub-byte quantized DNN inference [Paper]. 2023 IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, CA, USA (5 pages). External link

Alizadeh, R., Savaria, Y., & Nerguizian, C. (2022, October). Automatic Detection of People Getting Into a Bus in a SMART Public Transportation System [Paper]. 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2022), Glasgow, Scotland. External link

Abadi, A. F. E., Asghari, S. A., Marvasti, M. B., Abaei, G., Nabavi, M., & Savaria, Y. (2022). RLBEEP: Reinforcement-Learning-Based Energy Efficient Control and Routing Protocol for Wireless Sensor Networks. IEEE Access, 10, 44123-44135. External link

Ali, M., Hassan, A., Honarparvar, M., Nabavi, M., Audet, Y., Sawan, M., & Savaria, Y. (2022). A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges. IEEE Access, 10, 24540-24555. External link

Ali, M., Elsayed, A., Mendez, A., Savaria, Y., & Sawan, M. (2021). Contact and remote breathing rate monitoring techniques: a review. IEEE Sensors Journal, 21(13), 14569-14586. Available

Abuelnasr, A., Amer, M., Ragab, A., Gosselin, B., & Savaria, Y. (2021, May). Causal information prediction for analog circuit design using variable selection methods based on machine learning [Paper]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). External link

Alhousseiny, I., Ali, M., Ben-Hamida, N., Honarparvar, M., Sawan, M., & Savaria, Y. (2021, November). Delay-Locked Loop Based Multiphase Clock Generator for Time-Interleaved ADCs [Paper]. 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2021), Dubai, United Arab Emirates (4 pages). External link

Amer, M., Abuelnasr, A., Ragab, A., Hassan, A., Ali, M., Gosselin, B., Sawan, M., & Savaria, Y. (2021, May). Design and analysis of combined input-voltage feedforward and PI controllers for the buck converter [Paper]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). External link

Alizadeh, R., Savaria, Y., & Nerguizian, C. (2021, October). Human Activity Recognition and People Count for a SMART Public Transportation System [Paper]. 4th IEEE 5G World Forum (5GWF 2021), Montreal, Québec. External link

Akbari, M., Honarparvar, M., Savaria, Y., & Sawan, M. (2021). Power Bound Analysis of a Two-Step MASH Incremental ADC Based on Noise-Shaping SAR ADCs. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(8), 3133-3146. External link

AskariHemmat, M.H., Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (2021, May). RISC-V barrel processor for deep neural network acceleration [Paper]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). External link

Amer, M., Ali, M., Abuelnasr, A., Hassan, A., Nabavi, M., Savaria, Y., & Sawan, M. (2020, June). Fully integrated dual-channel gate driver and area efficient pid compensator for surge tolerant power sensor interface [Paper]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Qc, Canada. External link

Akbari, M., Honarparvar, M., Savaria, Y., & Sawan, M. (2020, October). OTA-free MASH 2-2 noise shaping SAR ADC: System and design considerations [Paper]. 52nd IEEE International Symposium on Circuits and Systems (ISCAS 2020) (5 pages). External link

Akbari, M., Honarparvar, M., Savaria, Y., & Sawan, M. (2020, June). OTA-free MASH Two-step Incremental ADC based on Noise Shaping SAR ADCs [Paper]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Qc, Canada. External link

Askarihemmat, M.H., Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (2020, May). RISC-V Barrel Processor for Accelerator Control [Paper]. 28th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2020), Fayetteville, AR (1 page). External link

Abuelnasr, A., Ali, M., Amer, M., Nabavi, M., Hassan, A., Gosselin, B., & Savaria, Y. (2020, October). Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2020), Sevilla, Spain (5 pages). External link

AskariHemmat Hossein, M., Savaria, Y., Jean-Pierre, D., Honari, S., Perone, C., Rouhier, L., & Cohen-Adad, J. (2019, October). Fixed-point u-net quantization for medical image segmentation [Paper]. 22nd International Conference on Medical Image Computing & Computer Assisted Intervention (MICCAI 2019), Shenzhen, China. Unavailable

Assaf, H., Savaria, Y., & Sawan, M. (2019, March). Memristor Emulators for an Adaptive DPE Algorithm: Comparative Study [Paper]. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2019), Hsinchu, Taiwan. External link

Ammar, M., Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2019). Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-trees (TDFTs). IEEE Access, 7, 29264-29276. External link

AskariHemmat, M.H., Honari, S., Rouhier, L., Perone, C. S., Cohen-Adad, J., Savaria, Y., & David, J. P. (2019, October). U-net fixed-point quantization for medical image segmentation [Paper]. 1st International Workshop on Hardware Aware Learning for Medical Imaging and Computer Assisted Intervention (HAL-MICCAI 2019), Shenzhen, China. External link

Ali, M., Nabavi, M., Hassan, A., Honarparvar, M., Savaria, Y., & Sawan, M. (2019, December). A versatile SoC/SiP sensor interface for industrial applications: Design considerations [Paper]. 31st International Conference on Microelectronics (ICM 2019), Cairo, Egypt. External link

Amer, M., Hassan, A., Ragab, A., Yacout, S., Savaria, Y., & Sawan, M. (2018, May). High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy. External link

Abubakr, A., Hassan, A., Ragab, A., Yacout, S., Savaria, Y., & Sawan, M. (2018, May). High-temperature modeling of the I-V characteristics of GaN150 HEMT using machine learning techniques [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italie (5 pages). External link

Ammar, M., Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2018, December). Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMC [Paper]. 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2018), Bordeaux, France. External link

Assaf, H., Savaria, Y., & Sawan, M. (2018, December). Vector matrix multiplication using crossbar arrays: a comparative analysis [Paper]. 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2018), Bordeaux, France. External link

Ammar, M., Hamad, G. B., Mohamed, O. A., Savaria, Y., & Velazco, R. (2016, September). Comprehensive vulnerability analysis of systems exposed to SEUs via probabilistic model checking [Paper]. 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2016), Bremen, Germany (4 pages). External link

Ammar, M., Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2017). System-Level Analysis of the Vulnerability of Processors Exposed to Single Event Upsets via Probabilistic Model Checking. IEEE Transactions on Nuclear Science, 64(9), 2523-2530. External link

Ammar, M., Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2016, September). Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking [Paper]. Forum on Specification and Design Languages (FDL 2016), Bremen, Germany (8 pages). External link

Alizadeh, R., & Savaria, Y. (2016, December). Performance analysis of a reduced complexity SCMA decoder exploiting a low-complexity maximum-likelihood approximation [Paper]. 23rd IEEE International Conference on Electronics Circuits and Systems (ICECS 2016), Monte Carlo, Monaco. External link

Alizadeh, R., Belanger, N., Savaria, Y., & Boyer, F.-R. (2016, June). Performance characterization of an SCMA decoder [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). External link

Alizadeh, R., Bélanger, N., Savaria, Y., & Frigon, J.-F. (2015, June). DPDK and MKL; enabling technologies for near deterministic cloud-based signal processing [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link

Abdollahifakhr, H., Bélanger, N., Savaria, Y., & Gagnon, F. (2015, June). Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link

Al-bayati, Z., Ait Mohamed, O., Rafay Hasan, S., & Savaria, Y. (2012, December). Design of a C-element based clock domain crossing interface [Paper]. 24th International Conference on Microelectronics (ICM 2012), Algiers, Algeria (4 pages). External link

Al-Bayati, Z., Ait Mohamed, O., Hasan, S. R., & Savaria, Y. (2012, May). A novel hybrid FIFO asynchronous clock domain crossing interfacing method [Paper]. 22nd Great Lakes Symposium on VLSI (GLSVLSI 2012), Salt Lake City, Utah. External link

Al-Bayati, Z., Ait Mohamed, O., Savaria, Y., & Boukadoum, M. (2012, June). Probabilistic model checking of clock domain crossing interfaces [Paper]. 10th IEEE International New Circuits and Systems Conference (NEWCAS 2012), Montréal, Québec. External link

Al-Terkawi Hasib, O., André, W., Blaquière, Y., & Savaria, Y. (2012, May). Propagating analog signals through a fully digital network on an electronic system prototyping platform [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. External link

Aubertin, P., Langlois, J. M. P., & Savaria, Y. (2012). Real-time computation of local neighborhood functions in application-specific instruction-set processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(11), 2031-2043. External link

Anane, A., Aboulhamid, E. M., & Savaria, Y. (2012, July). System modeling and multicore simulation using transactions [Paper]. International Conference on Embedded Computer Systems (SAMOS 2012), Samos, Grèce. External link

Allard, M., Grogan, P., Savaria, Y., & David, J. P. (2012, May). Two-level configuration for FPGA: A new design methodology based on a computing fabric [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. External link

Al-Terkawi Hasib, O., Sawan, M., & Savaria, Y. (2011). A low-power asynchronous step-down DCDC converter for implantable devices. IEEE Transactions on Biomedical Circuits and Systems, 5(3), 292-301. External link

Ayachi, D., Savaria, Y., & Thibeault, C. (2009, June). A configurable platform for MPSoCs based on application specific instruction set processors [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link

Aubertin, P., Mohammadi, H. M., Savaria, Y., & Langlois, J. M. P. (2009, June). High performance ASIP implementation of PBDI: a new intra-field deinterlacing method [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link

Anane, A., Aboulhamid, E. M., Vachon, J., & Savaria, Y. (2008, May). Modeling and simulation of complex heterogeneous systems [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, WA, United states. External link

Abderrahman, A., Savaria, Y., Khouas, A., & Sawan, M. (2007, August). Accurate testability analysis based-on multi-frequency test generation and a new testability metric [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. External link

Abderrahman, A., Savaria, Y., Khouas, A., & Sawan, M. (2007, December). New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco. External link

Adham, S. M. I., Savaria, Y., Antaki, B., & Xiong, N. (2000). Voltage excursion detection apparatus. (Patent no. US6100716). External link

Antaki, B., Savaria, Y., Saman, A., Xiong, N., Borrione, D., & Ernst, R. (1999, March). Design for testability method for CML digital circuits [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 1999), Munich, Germany. External link

Audet, D., Masson, S., & Savaria, Y. (1998, November). Reducing fault sensitivity of microprocessor-based systems by modifying workload structure [Paper]. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 1998), Austin, TX. External link

Antaki, B., Patenaude, S., Trognon, L., & Savaria, Y. (1997, June). Study on split-output TSPC CMOS circuits [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong. External link

Abderrahman, A., Savaria, Y., & Kaminska, B. (1996). Analyse, estimation et réduction du bruit de commutation simultanée. [Analysis, estimation and reduction of simultaneous switching noise]. Canadian Journal of Electrical and Computer Engineering, 21(4), 133-143. External link

Audet, D., Gagnon, N., & Savaria, Y. (1996, January). Implementing fault injection and tolerance mechanisms in multiprocessor systems [Paper]. IEEE Workshop on Defect and Fault Tolerance in VLSI (DFT 1996), Boston. External link

Audet, D., Gagnon, F., & Savaria, Y. (1996, January). Quantitative comparisons of TMR implementations in a multiprocessor system [Paper]. 3rd IEEE On-Line Testing Workshop, Biarritz. Unavailable

Audet, D., & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the host interface. (Technical Report). Unavailable

Audet, D., & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the routers, from a functional to a detailed implementation description. (Technical Report). Unavailable

Audet, D., Savaria, Y., & Arel, N. (1995). Effective ultra large scale integration (ULSI) architecture techniques: FATMOS, a fault-tolerant multiprocessor operating system. (Technical Report). Unavailable

Audet, D., & Savaria, Y. (1995). High-speed interconnections using true single-phase clocking. Journal of Microelectronic Systems Integration, 3(4), 247-257. Unavailable

Audet, D., & Savaria, Y. High-speed interconnections using true single-phase clocking [Paper]. 7th IEEE Annual International Conference on Wafer Scale Integration, San Francisco, Ca, USA. External link

Audet, D., & Savaria, Y. (1994). Architectural approach for increasing clock frequency and communication speed in monolithic WSI systems. IEEE Transactions on Components Packaging and Manufacturing Technology. Part B, Advanced Packaging, 17(3), 362-368. External link

Audet, D., Savaria, Y., & Arel, N. (1994, January). Architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems [Paper]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, California. External link

Abderrahman, A., Kaminska, B., & Savaria, Y. (1994, February). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits [Paper]. European Design and Test Conference, Paris, Fr. External link

Audet, D., Savaria, Y., & Arel, N. (1994). Pipelining communications in large VLSI/ULSI systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1), 1-10. External link

Audet, D., Savaria, Y., & Houle, J.-L. (1992). Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources. Parallel Computing, 18(2), 149-167. External link

Audet, D., Chouinard, G., Cyr, C., Houle, J.-L., & Savaria, Y. (1988). IMAGE2 : un circuit multiprocesseur pour le traitement parallèle. (Technical Report n° EPM-RT-88-35). Restricted access

Audet, D., Savaria, Y., & Houle, J.-L. (1988). Performance improvements of VLSI parallel systems, using dynamic concatenation of processing resources. (Technical Report n° EPM-RT-88-36). Restricted access

B

Bensalem, H., Blaquière, Y., & Savaria, Y. (2023). An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(3), 1144-1148. External link

Bensalem, H., Blaquiere, Y., & Savaria, Y. (2021, May). Acceleration of the secure hash algorithm-256 (SHA-256) on an FPGA-CPU cluster using OpenCL [Paper]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). External link

Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (2021). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models. In The Lognormality Principle and its Applications in e-Security, e-Learning and e-Health (Vol. 88, 309-325). External link

Berrima, S., Blaquiere, Y., & Savaria, Y. (2021). Ring-Oscillator Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Transactions on Instrumentation and Measurement, 70, 1-10. External link

Berrima, S., Blaquiere, Y., & Savaria, Y. (2020). Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices & Systems, 14(8), 1243-1252. External link

Bensalem, H., Blaquiere, Y., & Savaria, Y. (2020). In-FPGA instrumentation framework for openCL-based designs. IEEE Access, 8, 212979-212994. Available

Bensenouci, M. A., Ali, M., Escid, H., Savaria, Y., & Sawan, M. (2020, December). A VCO-Based Nonuniform Sampling ADC Using a Slope-Dependent Pulse Generator [Paper]. 32nd International Conference on Microelectronics (ICM 2020), Aqaba, Jordan (4 pages). External link

Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). HPQS: A fast, high-capacity, hybrid priority queuing system for high-speed networking devices. IEEE Access, 7, 130672-130684. Available

Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). A high-speed, scalable, and programmable traffic manager architecture for flow-based networking. IEEE Access, 7, 2231-2243. Available

Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (2019, May). Bit-slicing FPGA accelerator for quantized neural networks [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). External link

Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (2019, June). Combining Interval Arithmetic with the Branch and Bound Algorithm for Delta-lognormal Parameter Extraction [Paper]. International Conference of the International Graphonomics Society, Cancun, Mexico (5 pages). Unavailable

Benyoussef, M., Thibeault, C., & Savaria, Y. (2019, May). A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). External link

Bensalem, H., Blaquiere, Y., & Savaria, Y. (2019, May). Toward in-system monitoring of OpenCL-based designs on FPGA [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). External link

Benacer, I., Boyer, F.-R., & Savaria, Y. (2018, May). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). External link

Berrima, S., Blaquière, Y., & Savaria, Y. (2018). Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integration, 62, 159-169. External link

Benacer, I., Boyer, F.-R., & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952. External link

Benacer, I., Boyer, F.-R., & Savaria, Y. (2018, June). HPQ: a high capacity hybrid priority queue architecture for high-speed network switches [Paper]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. External link

Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (2018, May). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models [Paper]. International Conference on Pattern Recognition and Artificial Intelligence (ICPRAI 2018), Montréal, Québec. Unavailable

Benacer, I., Boyer, F.-R., & Savaria, Y. (2017, June). A high-speed traffic manager architecture for flow-based networking [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link

Berrima, S., Blaquière, Y., & Savaria, Y. (2017, May). A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD (4 pages). External link

Berrima, S., Blaquiere, Y., & Savaria, Y. (2017, August). Sub-ps resolution programmable delays implemented in a Xilinx FPGA [Paper]. 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Boston, MA. External link

Bany Hamad, G., Kazma, G., Mohamed, O. A., & Savaria, Y. (2016, November). Efficient and accurate analysis of single event transients propagation using SMT-based techniques [Paper]. 35th International Conference on Computer-Aided Design (ICCAD 2016), Austin, TX (7 pages). External link

Benacer, I., Boyer, F.-R., Bélanger, N., & Savaria, Y. (2016, June). A fast systolic priority queue architecture for a flow-based Traffic Manager [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). External link

Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (2016, September). SMT-based reliability-aware synthesis for single event transients tolerant combinational circuits [Poster]. Radiation Effects on Components & Systems Conference (RADECS 2016), Bremen, Germany. Unavailable

Blaquiere, Y., Basile-Bellavance, Y., Berrima, S., & Savaria, Y. (2014, June). Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, VIC, Australia (4 pages). External link

Bany Hamad, G., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (2014). New insights into the single event transient propagation through static and TSPC logic. IEEE Transactions on Nuclear Science, 61(4), 1618-1627. External link

Bouanen, S., Thibeault, C., Savaria, Y., & Tremblay, J. P. (2013, October). Fault tolerant smart transducer interface for safety-critical avionics applications [Paper]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. External link

Blaquièere, Y., Savaria, Y., Basile-Bellavance, Y., Valorge, O., Lahkssassi, A., André, W., Laflamme Mayer, N., Bougataya, M., & Sawan, M. (2013). Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical signal propagation. (Patent Application no. US20130285739). External link

Baratli, K., Lakhssassi, A., Blaquière, Y., & Savaria, Y. (2013, June). A netlist pruning tool for an electronic system prototyping platform [Paper]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. External link

Bany Hamad, G., Ait Mohamed, O., Rafay Hasan, S., & Savaria, Y. (2012, May). Identification of soft error glitch-propagation paths: Leveraging SAT solvers [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. External link

Boulais, E., Fantoni, J., Chateauneuf, A., Savaria, Y., & Meunier, M. (2011). Laser-induced resistance fine tuning of integrated polysilicon thin-film resistors. IEEE Transactions on Electron Devices, 58(2), 572-575. External link

Bany Hamad, G., Mohamed, O. A., Hasan, S. R., & Savaria, Y. (2011, December). SEGP-finder: Tool for identification of soft error glitch-propagating paths at gate level [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link

Berriah, O., Bougataya, M., Lakhssassi, A., Blaquiere, Y., & Savaria, Y. (2010, June). Thermal analysis of a miniature electronic power device matched to a silicon wafer [Paper]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. External link

Bougataya, M., Berriah, O., Lakhssassi, A., Dahmane, A.-O., Blaquiere, Y., Savaria, Y., Norman, R., & Prytula, R. (2010, December). Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit [Paper]. 17th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece. External link

Basile-Bellavance, Y., Blaquiere, Y., & Savaria, Y. (2009, June). Faults diagnosis methodology for the WaferNet interconnection network [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link

Bafumba-Lokilo, D., Savaria, Y., & David, J. P. (2009, October). Generic array-based MPSoC architecture [Paper]. 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada. External link

Beucher, N., Belanger, N., Savaria, Y., & Bois, G. (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), 155-165. External link

Bui, H. T., & Savaria, Y. (2008). Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-Ghz Frequency-Locked Loop. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(3), 766-774. External link

Bafumba-Lokilo, D., Savaria, Y., & David, J. P. (2008, June). Generic crossbar network on chip for FPGA MPSoCs [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link

Basile-Bellavance, Y., Lepercq, E., Blaquiere, Y., & Savaria, Y. (2008, August). Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL [Paper]. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008). External link

Bougataya, M., Lakhsasi, A., Norman, R., Prytula, R., Blaquière, Y., & Savaria, Y. (2008, May). Steady state thermal analysis of a reconfigurable wafer-scale circuit board [Paper]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008), Niagara Falls, Ont.. External link

Boulais, É., Binet, V., Degorce, J.-Y., Wild, G., Savaria, Y., & Meunier, M. (2008). Thermodynamics and Transport Model of Charge Injection in Silicon Irradiated by a Pulsed Focused Laser. IEEE Transactions on Electron Devices, 55(10), 2728-2735. External link

Benamrane, I., & Savaria, Y. (2007, August). Design techniques for high speed current steering DACs [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montreal, Qc, Canada (4 pages). External link

Blaquiere, Y., Savaria, Y., & El Fouladi, J. (2007, December). Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco (4 pages). External link

Binet, V., Savaria, Y., Meunier, M., & Gagnon, Y. (2007, May). Modeling the substrate noise injected by a DC-DC converter [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), Phoenix-Scottsdale, AZ. External link

Boyer, F.-R., Epassa, H. G., & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290. External link

Bui, H. T., & Savaria, Y. (2006, April). High speed differential pulse-width control loop based on frequency-to-voltage converters [Paper]. 16th ACM Great Lakes Symposium on VLSI (GLSVLSI 2006), Philadelphia, USA. External link

Beucher, N., Belanger, N., Savaria, Y., & Bois, G. (2006, October). Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor [Paper]. IEEE Workshop on Signal Processing Systems Design and Implementation, Banff, AB, Canada. External link

Belanger, N., & Savaria, Y. (2006, June). On the design of a double precision logarithmic number system arithmetic unit [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link

Bui, H. T., & Savaria, Y. (2005, July). Design and analysis of XOR gates for high-speed and low-jitter applications [Paper]. 9th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2005), Orlando, Floride. Unavailable

Bui, H. T., & Savaria, Y. (2005, July). A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in Socs [Paper]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. External link

Bui, H. T., & Savaria, Y. (2005, June). High-speed differential frequency-to-voltage converter [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005). External link

Bui, H. T., & Savaria, Y. (2004, July). 10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 mu m CMOS [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link

Boland, J. F., Chureau, A., Thibeault, C., Savaria, Y., Gagnon, F., & Zilic, Z. (2004, June). An efficient methodology for design and verification of an equalizer for a software defined radio [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Boudjella, A., Jin, Z., & Savaria, Y. (2004). Electrical Field Analysis of Nanoscale Field Effect Transistors. Japanese Journal of Applied Physics, 43(6), 3831-3837. External link

Bui, H. T., & Savaria, Y. (2004, May). Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. External link

Bui, T., & Savaria, Y. (2004, June). Shunt-peaking of MCML gates using active inductors [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Bougataya, M., Lakhasasi, A., Savaria, Y., & Massicotte, D. (2004, May). Thermo-mechanical stress analysis of VLSI devices by partially coupled finite element method [Paper]. 18th Annual Canadian Conference on Electrical and Computer Engineering (CCEC 2004), Niagara Falls, Ontario. External link

Boyer, F.-R., Epassa, H. G., Pontikakis, B., Savaria, Y., & Ling, W. (2004, June). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Bissou, J. P., & Savaria, Y. (2003, January). Conception de haut niveau d'une plate-forme SOC pour la conversion de protocoles réseaux [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). External link

Beaudin, S., Marceau, R. J., Bois, G., Savaria, Y., & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112. External link

Boudjella, A., Jin, Z.-F., & Savaria, Y. (2003, October). Electrical field analysis of nanoscaled field effect transistors [Paper]. International Microprocesses and Nanotechnology Conference, Tokyo, Japan. External link

Bissou, J. P., Dubois, M., Savaria, Y., & Bois, G. (2003, December). High-speed system bus for a SoC network processing platform [Paper]. 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt. External link

Bougataya, M., Lakhsasi, A., Savaria, Y., & Massicotte, D. (2003, January). Stress and distortion behavior for VLSI steady state thermal analysis [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). External link

Bendali, A., & Savaria, Y. (2002, May). Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. External link

Boyer, F.-R., Aboulhamid, E. M., & Savaria, Y. (2001, August). Minimizing sensitivity to clock skew variations using level sensitive latches [Paper]. 15th European Conference on Circuit Theory and Design (ECCTD 2001), Espoo, Finland. Unavailable

Boyer, F.-R., Aboulhamid, E. M., Savaria, Y., & Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), 516-532. External link

Boyer, F.-R., Aboulhamid, E. M., & Savaria, Y. (2000, January). Efficient verification method for a class of multi-phase sequential circuits [Paper]. 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000). External link

Bosi, B., Bois, G., & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308. External link

Boyer, F. R., Abiylhamid, E. M., Savaria, Y., & Bennour, I. E. (1998, January). Optical design of synchronous circuits using software pipeling techniques [Paper]. VLSI in Computers and Processors, Austin. External link

Bélanger, N., Antaki, B., & Savaria, Y. (1997, July). An algorithm for fast array transfers [Paper]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Unavailable

Bois, G., Bosi, B., & Savaria, Y. (1997, January). High performance reconfigurable coprocessor for digital signal processing [Paper]. 14th Annual International Conference of the Mentor Graphics Users' Group, Portland, Oregon. Unavailable

Belabbes, N.-E., Guterman, A. J., Savaria, Y., & Dagenais, M. (1996). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(2), 143-152. External link

Belhaouane, A., Savaria, Y., & Kaminska, B. (1996, January). Reconstruction method for data acquisition systems with randomly distributed jitter [Paper]. 2nd IEEE International Mixed Signal Testing Workshop. Unavailable

Belhaouane, A., Savaria, Y., Kaminska, B., & Massicotte, D. (1996). Reconstruction method for jitter tolerant data acquisition system. Journal of Electronic Testing: Theory and Applications, 9(1-2), 177-185. External link

Blaquiere, Y., Dagenais, M., & Savaria, Y. (1996). Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), 244-255. External link

Barwicz, A., Massicotte, D., Savaria, Y., Pango, P. A., & Morawski, R. Z. (1995). An application-specific processor dedicated to kalman-filter-based correction of spectrometric data. IEEE Transactions on Instrumentation and Measurement, 44(3), 720-724. External link

Belzile, J., Savaria, Y., Haccoun, D., & Chalifoux, M. (1995). Bounds on the performance of partial selection networks. IEEE Transactions on Communications, 43(2-4), 1800-1809. External link

Blaquiere, T., Gagné, G., Savaria, Y., & Évéquoz, C. (1995). A new efficient algorithmic-based seu tolerant system architecture. IEEE Transactions on Nuclear Science, 42(6), 1599-1606. External link

Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M.-A., & Morawski, R. Z. (1994, May). An application-specific processor dedicated to Kalman-filter-based correction of spectrometric data [Paper]. IEEE Instrumentation and Measurement Technology Conference (IMTC 1994), Hamamatsu, Japan. External link

Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M. A., & Morawski, R. Z. (1994). An integrated structure for kalman-filter-based measurand reconstruction. IEEE Transactions on Instrumentation and Measurement, 43(3), 403-410. External link

Bélanger, N., Haccoun, D., & Savaria, Y. (1994). A multiprocessor architecture for multiple path stack sequential decoders. IEEE Transactions on Communications, 42(2-4, pt.2), 951-957. External link

BenHamida, N., Kaminska, B., & Savaria, Y. (1994, May). Pseudo-random vector compaction for sequential testability [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. External link

Belabbes, N., Guterman, A., Savaria, Y., & Dagenais, M. (1992, May). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. External link

Blaquiere, Y., & Savaria, Y. (1987). Area Overhead Analysis of SEF: A Design Methodology for Tolerating SEU. IEEE Transactions on Nuclear Science, 34(6), 1481-1486. External link

C

Chebli, R., Sawan, M., El-Sankary, K., & Savaria, Y. (2010). High-voltage DMOS integrated circuits using floating-gate protection technique. Analog Integrated Circuits and Signal Processing, 62(2), 223-235. External link

Chebli, R., Sawan, M., Savaria, Y., & El-Sankary, K. (2007, May). High-voltage DMOS integrated circuits with floating gate protection technique [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, USA. External link

Castonguay, A., & Savaria, Y. (2006, May). Architecture of a hypertransport tunnel [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. External link

Chureau, A., Savaria, Y., Boland, J.-F., Zilic, Z., Thibeault, C., & Gagnon, F. (2006, June). Building heterogeneous functional prototypes using articulated interfaces [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link

Cantin, M.-A., Savaria, Y., Prodanos, D., & Lavoie, P. (2006). A metric for automatic word-length determination of hardware datapaths. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10), 2228-31. External link

Chebli, R., Sawan, M., & Savaria, Y. (2005, December). Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results [Paper]. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2005), Tunisie. External link

Castonguay, A., & Savaria, Y. (2005, June). A Hypertransport Chip-to-Chip Interconnect Tunnel Developed Using Systemc [Paper]. 16th International Workshop on Rapid System Prototyping, Montréal, Québec. External link

Catudal, S., Cantin, M. A., & Savaria, Y. (2005, May). Parameters Estimation Applied to Automatic Video Processing Algorithms Validation [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link

Chebli, R., Sawan, M., & Savaria, Y. (2005, August). A programmable positive and negative high-voltage DC-DC converter dedicated for ultrasonic applications [Paper]. 48th Midwest Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio. External link

Chureau, A., Savaria, Y., & Aboulhamid, E. M. (2005, March). The Role of Model-Level Transactors and Uml in Functional Prototyping of Systems-on-Chip: a Software-Radio Application [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2005), Munich, Germany. External link

Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. (2005). Scheduling and Optimal Register Placement for Synchronous Circuits Derived Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 10(2), 187-204. External link

Calbaza, D. E., Cordos, I., Seth-Smith, N., & Savaria, Y. (2004, May). An Adpll Circuit Using a Ddps for Genlock Applications [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2004). External link

Cantin, M. A., Savaria, Y., & Velazco, R. (2004). An automatic word length determination method. WSEAS Transactions on Information Science & Applications, 1(5), 1440-1448. Unavailable

Chureau, A., Savaria, Y., & Aboulhamid, E. M. (2004, July). Interface-based design of systems-on-chip using UML-RT [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link

Catudal, S., Cantin, M.-A., & Savaria, Y. (2004). Performance driven validation applied to video processing. WSEAS Transactions on Electronics, 1(3), 568-575. Unavailable

Cantin, M. A., Regimbal, S., Catudal, S., & Savaria, Y. (2004). A Unified Environment to Assess Image Quality in Video Processing. Journal of Circuits, Systems and Computers, 13(6), 1289-1306. External link

Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003). Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), 346-351. External link

Catudal, S., Cantin, M. A., & Savaria, Y. (2003). Performance driven validation applied to viseo processing. WSEAS Transactions on Electronics, 1(3), 568-574. Unavailable

Chabini, N., Chabini, I., Aboulhamid, E. M., & Savaria, Y. (2003, January). Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs [Paper]. Great Lakes Symposium on VLSI (GLSVLSI 2003), Washington, D. C., USA. External link

Cantin, M.-A., Savaria, Y., & Lavoie, P. (2002, May). A comparison of automatic word length optimization procedures [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. External link

Calbaza, D. E., & Savaria, Y. (2002). A Direct Digital Period Synthesis Circuit. IEEE Journal of Solid-State Circuits, 37(8), 1039-1045. External link

Chabini, N., Aboulhamid, E. M., Chabini, I., & Savaria, Y. Minimizing the Number of Phases in Clocked Digital Designs Derived Using Modulo Scheduling Techniques [Paper]. Icm 2002: 14th International Conference on Microelectronics. External link

Cantin, M.-A., Savaria, Y., Prodanos, D., & Lavoie, P. (2001, May). An automatic word length determination method [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, NSW, Australia. External link

Chabini, N., Aboulhamid, M., & Savaria, Y. (2001, January). Determining schedules for reducing power consuption using mulyiple supply voltages [Paper]. International Conference on Computer Design (ICCD 2001), Austin, Texas. External link

Calbaza, D. E., & Savaria, Y. (2001). Direct Digital Frequency Synthesis of Low-Jitter Clocks. IEEE Journal of Solid-State Circuits, 36(3), 570-572. External link

Chabini, N., Aboulhamid, M., & Savaria, Y. (2001, January). Efficient methods for reducing register and phase requirements for synchronous circuits derived using software pipeling techniques [Paper]. European Conference on Circuit Theory and Design, Espoo, Finland. Unavailable

Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, January). Fast method for determining an efficient bound on the optimal solution of the cost-to-time ratio problem [Paper]. 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001) and 7th International Conference in Information Systems Analysis and Synthesis (ISAS 2001), Orlando, Floride. Unavailable

Chabini, N., & Savaria, Y. (2001, January). Methods for optimizating register placement in synchronous circuits derived using software pipelining techniques [Paper]. 14th International Symposium on System Synthesis (ISSS 2001), Montréal, Québec. External link

Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, January). Minimizing registe requirements for synchronous circuits derived using software pipelining techniques [Paper]. 13th International Conference on Microelectronics (ICM 2001), Rabat, Maroc. External link

Chabini, N., Aboulhamid, E. M., & Savaria, Y. (2001, April). Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques [Paper]. IEEE Computer Society Workshop on VLSI (WVLSI 2001), Orlando, FL, United states. External link

Cantin, M.-A., Blaquière, Y., Savaria, Y., Lavoie, P., & Granger, É. (2000, May). Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland. External link

Calbaza, D. E., & Savaria, Y. (2000, May). Direct digital frequency synthesis of low-jitter clocks [Paper]. IEEE Custom Integrated Circuits Conference, Orlando, FL, USA. External link

Calbaza, D. E., & Savaria, Y. (2000, October). A direct digitally delay generator [Paper]. 23rd International Semiconductor Conference (CAS 2000), Sinaia, Romania. External link

Calbaza, D. E., & Savaria, Y. (2000, January). Jitter model of direct digital synthesis clock generators [Paper]. TCAS-I 2000. Unavailable

Cousineau, C., Laperle, F., Savaria, Y., Pocek, K. L., & Arnold, J. M. (1999, April). Design of a JTAG based run time reconfigurable system [Paper]. 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA. External link

Calbaza, D. E., & Savaria, Y. (1999, May). Jitter model of direct digital synthesis clock generators [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. External link

Cantin, M.-A., Blaquière, Y., Savaria, Y., Granger, É., & Lavoie, P. (1998, May). Implementation fo the Fuzzy ART neural network for fast clustering of radar pulses [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1998), Monterey, CA, USA. External link

Chabini, N., Bennour, I. E., Aboulhamid, E. M., & Savaria, Y. (1998, January). Static method for system performance estimation [Paper]. 10th International Conference on Microelectronics. External link

Crespo, J.-F., Lavoie, P., & Savaria, Y. (1994, May). Fast convergence with low precision weights in ART1 networks [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. External link

Crepeau, J., Thibeault, C., & Savaria, Y. (1993, October). Some results on yield and local design rule relaxation [Paper]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1993), Venice, Italy. External link

Currie, J. F., Savaria, Y., & Dionne, J.-P. (1988). Réalisation d'un diviseur de fréquence numérique sur AsGa. (Technical Report n° EPM-RT-88-03). Restricted access

D

Dufour, J., Savaria, Y., & David, J. P. Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries [Paper]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). External link

Dupuis, T., Fournier, Y., AskariHemmat, M.H., Zarif, N. E., Leduc-Primeau, F., David, J. P., & Savaria, Y. (2023, June). Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference [Paper]. 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). External link

Deca, R., Cherkaoui, O., & Savaria, Y. (2014, September). Constraint-based configuration complexity model for autonomic network configuration management [Paper]. Global Information Infrastructure and Networking Symposium (GIIS 2014), Montréal, Québec. External link

Deca, R., Cherkaoui, O., & Savaria, Y. (2012). Rule-based network service provisioning. Journal of Networks, 7(10), 1493-1504. External link

Deca, R., Cherkaoui, O., Savaria, Y., & Slone, D. (2007). Constraint-Based Model Service for Network Provisioning. Annales des télécommunications, 62(7-8), 847-870. External link

Dubois, M., Savaria, Y., Haccoun, D., & Belanger, N. (2006). Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders. IEE Proceedings. Circuits, Devices and Systems, 153(3), 207-213. External link

Deslauriers, F., Langevin, M., Bois, G., Savaria, Y., & Paulin, P. (2006, June). RoC: a scalable network on chip based on the token ring concept [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link

Deca, R., Mahrez, O., Cherkaoui, O., Savaria, Y., & Slone, D. (2005, August). Contributions to automated testing of network service interactions [Paper]. 5e Colloque International sur les nouvelles technologies de la répartition (NOTERE 2005), Gatineau, Québec. Unavailable

Dubois, M., Savaria, Y., & Bois, G. (2005, April). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands [Paper]. IEEE SoutheastCon 2004, Fort Lauderdale, Florida, USA. External link

Dang, H., Sawan, M., & Savaria, Y. (2005, May). A Novel Approach for Implementing Ultra-High Speed Flash Adc Using Mcml Circuits [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link

Dubois, M., Bois, G., & Savaria, Y. (2004). Double profiling methodology for video processing platform. WSEAS Transactions on Computers, 3(6), 1802-1807. Unavailable

Duval, O., Lafrance, L. P., Savaria, Y., & Desjardins, P. (2004, August). An Integrated Test Platform for Nanostructure Electrical Characterization [Paper]. International Conference on Mems, Nano and Smart Systems (ICMENS 2004), Banff, Canada. External link

Dubois, M., Savaria, Y., & Haccoun, D. (2004, June). On low power shift register hardware realizations for convolutional encoders and decoders [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Duval, O., & Savaria, Y. (2004, May). An on-chip delay measurements module for nanostructures characterization [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. External link

Dido, J., Geraudie, N., Loiseau, L., Payeur, O., Savaria, Y., & Poirier, D. (2002, February). A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs [Paper]. 10th ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2002). External link

Donfack, C., Sawan, M., & Savaria, Y. (2000, January). Fully integrated AC impedance measurement technique for implantable electrical stimulation applications [Paper]. 5th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 2000), Denmark. Unavailable

Donfack, C., Sawan, M., & Savaria, Y. (2000). Implantable Measurement Technique Dedicated to the Monitoring of Electrode-Nerve Contact in Bladder Stimulators. Medical & Biological Engineering & Computing, 38(4), 465-468. External link

Donfack, C., Sawan, M., & Savaria, Y. (2000, January). Techniques de caractérisation de l'interface électrode-tissus [Paper]. 2nd Symposium on Advanced Biomaterials (ISAB 2000), Montréal, Québec. Unavailable

Donfack, C., Sawan, M., & Savaria, Y. (1999, January). Efficient monitoring of electrodes-nerve contacts during FNS of the bladder [Paper]. 4th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 1999), Sendai, Japon. Unavailable

Dahmani, A., Savaria, Y., & Kaminska, B. (1992, May). Standard cell placement with Dynamic Clouds method [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. External link

E

El-Zarif, N., Amer, M., Ali, M., Hassan, A., Oukaira, A., Fayomi, C., & Savaria, Y. (2024). Calibration of ring oscillator-based integrated temperature sensors for power management systems. Sensors, 24(2), 440 (17 pages). Available

Elbediwy, M., Pontikakis, B., David, J. P., & Savaria, Y. (2023). A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access, 11, 61422-61436. Available

El-Zarif, N., Ali, M., Amer, M., Hassan, A., Oukaira, A., Lakhssassi, A., Fayomi, C. J. B., & Savaria, Y. (2022, June). Investigation of Different Integrated Temperature Monitoring Sensors for High-Voltage SoC DC-DC Converters [Paper]. 20th IEEE International Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, QC, Canada. External link

Ehmer, J., Granado, B., Denoulet, J., Savaria, Y., & David, J. P. (2022, June). Low complexity shallow neural network with improved false negative rate for cyber intrusion detection systems [Paper]. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada. External link

Eddine, T. D., Oukaira, A., Hassan, A., Savaria, Y., & Lakhssassi, A. (2021, June). Foster-based Transient Thermal Analysis of SiP for Thermomechanical Studies [Paper]. 19th IEEE International New Circuits and Systems Conference (NEWCAS 2021), Toulon, France (4 pages). External link

Ettahri, O., Oukaira, A., Ali, M., Hassan, A., Nabavi, M., Savaria, Y., & Lakhssassi, A. (2020). A Real-Time Thermal Monitoring System Intended for Embedded Sensors Interfaces. Sensors, 20(19), 5657 (16 pages). Available

El-Zarif, N., Ali, M., Hassan, A., Nabavi, M., Fayomi, C. J. B., & Savaria, Y. (2020, February). A High Efficiency and Fast Response PLL Based Buck Converter: Implementation and Simulation [Paper]. IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS 2020), San Jose, Costa Rica (4 pages). External link

El Fouladi, J., Lu, Z., Savaria, Y., & Martel, S. (2007, August). An integrated biosensor for the detection of bio-entities using magnetotactic bacteria and CMOS technology. [Paper]. 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2007), Lyon, France. External link

El fouladi, J., André, W., Savaria, Y., & Martel, S. (2006, August). System design of an integrated measurement electronic subsystem for bacteria detection using and electrode array and MC-1 magnetotactic bacteria [Paper]. International Workshop on Computer Architecture for Machine Perception and Sensing (CAMP 2006), Montréal, Québec. External link

Epassa, H. G., Boyer, F.-R., & Savaria, Y. (2005, May). Implementation of a Cycle by Cycle Variable Speed Processor [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link

F

Faraji, A., Sadrossadat, S. A., Moftakharzadeh, A., Nabavi, M., & Savaria, Y. (2023). Deep Independent Recurrent Neural Network Technique for Modeling Transient Behavior of Nonlinear Circuits. IEEE Transactions on Components, Packaging and Manufacturing Technology, 13(5), 688-699. External link

Faraji, A., Sadrossadat, S. A., Yazdian-Dehkordi, M., Nabavi, M., & Savaria, Y. (2022). A Hybrid Approach Based on Recurrent Neural Network for Macromodeling of Nonlinear Electronic Circuits. IEEE Access, 10, 127996-128006. External link

Fiorentino, M., Thibeault, C., & Savaria, Y. (2021). Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow. IET Computers & Digital Techniques, 15(6), 409-426. Available

Foroushani, A. N., Assaf, H., Noshahr, F. H., Savaria, Y., & Sawan, M. (2020, October). Analog circuits to accelerate the relaxation process in the equilibrium propagation algorithm [Paper]. 52nd IEEE International Symposium on Circuits and Systems (ISCAS 2020) (5 pages). External link

Fiorentino, M., Thibeault, C., Savaria, Y., Gagnon, F., Awad, T., Morrissey, D., & Laurence, M. (2019, May). AnARM: a 28nm energy efficient ARM processor based on Octasic asynchronous technology [Paper]. 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan. External link

Fradj, B., Wolff, B., Bélanger, N., & Savaria, Y. (2018, May). Implementation of a cache-based IPv6 lookup system with hashing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (4 pages). External link

Fiorentino, M., Savaria, Y., & Thibeault, C. (2017, June). FPGA implementation of Token-based Self-timed processors: A case study [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link

Fiorentino, M., Savaria, Y., Thibeault, C., & Gervais, P. (2016, May). A practical design method for prototyping self-timed processors using FPGAs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. External link

Fiorentino, M., Al-Terkawi, O., Savaria, Y., & Thibeault, C. (2015, June). Self-timed circuits FPGA implementation flow [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link

Farah, R., Gan, Q., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (2014). A computationally efficient importance sampling tracking algorithm. Machine Vision and Applications, 25(7), 1761-1777. External link

Fischer, A., Plamondon, R., Savaria, Y., Riesen, K., & Bunke, H. (2014, August). A Hausdorff heuristic for efficient computation of graph edit distance [Paper]. Joint IAPR International Workshop on Structural, Syntactic, and Statistical Pattern Recognition (S+SSPR 2014), Joensuu, Finland. External link

Fischer, A., Plamondon, R., O'Reilly, C., & Savaria, Y. (2014, September). Neuromuscular representation and synthetic generation of handwritten whiteboard notes [Paper]. 14th International Conference on Frontiers in Handwriting Recognition (ICFHR 2014), Crete, Greece. External link

Farah, R., Gan, Q., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (2011, December). A tracking algorithm suitable for embedded systems implementation [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link

Fouzar, Y., Savaria, Y., & Sawan, M. (2002, May). A CMOS phase-locked loop with an auto-calibrated VCO [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. External link

Fouzar, Y., Savaria, Y., & Sawan, M. (2001, May). A new controlled gain phase-locked loop technique [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, NSW, Australia. External link

Fouzar, Y., Sawan, M., & Savaria, Y. CMOS Wide-Swing Differential VCO for Fully Integrated Fast PLL [Paper]. 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000). External link

Fouzar, Y., Sawan, M., & Savaria, Y. (2000, May). A new fully integrated CMOS phase-locked loop with low jitter and fast lock time [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland. External link

Fouzar, Y., Sawan, M., & Savaria, Y. (2000, December). Very short locking time PLL based on controlled gain technique [Paper]. 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000), Jounieh, Lebanon. External link

Fouzar, Y., Sawan, M., & Savaria, Y. (1998, December). A BiCMOS wide-lock range fully integrated PLL [Paper]. 10th International Conference on Microelectronics, Monastir, Tunisia. External link

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Ghaffari, A., Asgharian, M., & Savaria, Y. (2023). Statistical Hardware Design With Multi-Model Active Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11 pages. External link

Ghaffari, A., & Savaria, Y. (2021). Efficient Design Space Exploration of OpenCL Kernels for FPGA Targets Using Black Box Optimization. IEEE Access, 9, 136819-136830. External link

Ghaffari, A., & Savaria, Y. (2020). CNN2Gate: an implementation of convolutional neural networks inference on FPGAs with automated design space exploration. Electronics, 9(12), 23 pages. Available

Ghaffari, A., Leonardon, M., Cassagne, A., Leroux, C., & Savaria, Y. (2019). Toward high-performance implementation of 5G SCMA algorithms. IEEE Access, 7, 10402-10414. External link

Gemieux, M., Li, M., Savaria, Y., David, J. P., & Zhu, G. (2018). A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access, 6, 62826-62839. External link

Gémieux, M., Savaria, Y., David, J. P., & Zhu, G. (2017, May). A cache-coherent heterogeneous architecture for low latency real time applications [Paper]. 20th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2017), Toronto, ON, Canada. External link

Ghaffari, A., Leonardon, M., Savaria, Y., Jego, C., & Leroux, C. (2017, June). Improving performance of SCMA MPA decoders using estimation of conditional probabilities [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link

Gémieux, M., Savaria, Y., Zhu, G., & Frigon, J.-F. (2016, June). Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). External link

Guillemot, M., Nguyen, H., Bougataya, M., Blaquiere, Y., Lakhssassi, A., Shields, M., & Savaria, Y. (2016). Wafer-scale rapid electronic systems prototyping platform: User support tools and thermo-mechanical validation. In Novel Advances in Microsystems Technologies and Their Applications (67-100). External link

Gan, Q. F., Langlois, J. M. P., & Savaria, Y. (2014). Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations. Journal of Signal Processing Systems for Signal Image and Video Technology, 75(3), 191-202. External link

Gan, Q., Langlois, J. M. P., & Savaria, Y. (2014). A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems. Circuits, Systems & Signal Processing, 33(11), 3591-3602. External link

Gill, D. C., Langlois, J. M. P., & Savaria, Y. (2013, October). Accelerating a modified gaussian pyramid with a customized processor [Paper]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2013), Cagliari, Italy. External link

Gan, Q., Langlois, J. M. P., & Savaria, Y. (2013). Parallel array histogram architecture for embedded implementations. Electronics Letters, 49(2), 99-101. External link

Gan, Q., Langlois, J. M. P., & Savaria, Y. (2013, August). A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor [Paper]. 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2013), Columbus, OH, USA. External link

Guillemot, M., Blaquière, Y., & Savaria, Y. (2013, May). Software Rendering Methods to Display Wafer Scale Integrated Circuit Dataset [Paper]. 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2013), Regina, Sask, CAN. External link

Gil, D. C., Farah, R., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (2011, May). Comparative analysis of contrast enhancement algorithms in surveillance imaging [Paper]. IEEE International Symposium of Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil. External link

Gagnon, F., Savaria, Y., Dumais, P., Ammari, M. L., & Thibeault, C. (2010). Multiequalizer unit used for telecommunications has decision unit, which receives corresponding synchronized signals and choose one synchronized signal that matches with predetermined transmission performance criterion signal. (Patent no. US7693490). External link

Gorse, N., Belanger, P., Chureau, A., Aboulhamid, E. M., & Savaria, Y. (2007). A High-Level Requirements Engineering Methodology for Electronic System-Level Design. Computers & Electrical Engineering, 33(4), 249-268. External link

Grou-Szabo, R., Ghattas, H., Savaria, Y., & Nicolescu, G. (2005, July). Component-Based Methodology for Hardware Design of a Dataflow Processing Network [Paper]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. External link

Gorse, N., Aboulhamid, E. M., & Savaria, Y. (2004, July). Consistency validation of high-level requirements [Paper]. 4th International Workshop on System on Chip for Real Time Applications (IWSOC 2004), Banff. External link

Gorse, N., Metzger, M., Lapalme, J., Aboulhamid, E. M., Savaria, Y., & Nicolescu, G. (2004, December). Enhancing ESys.Net with a semi-formal verification layer [Paper]. 16th International Conference on Microelectronics (ICM 2004), Tunisie. External link

Gorse, N., Bélanger, P., Aboulhamid, E. M., & Savaria, Y. (2004, December). Mixing linguistic and formal techniques for high-level requirements engineering [Paper]. 16th International Conference on Microelectronics (ICM 2004), Tunisie. External link

Granger, E., Catudal, S., Grou, R., Mbaye, M. M., & Savaria, Y. (2004, September). On current strategies for hardware acceleration of digital image restoration filters [Paper]. 4th WSEAS International Conference on Signal, Speech and Image Processing (ICOSSIP 2004), Izmir, Turquie. External link

Ghattas, H., & Savaria, Y. (2003, January). Design of dedicated low complexity embedded processors for SOC network processing applications [Paper]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Unavailable

Granger, E., Catudal, S., Grou, R., Mbaye, M. M., & Savaria, Y. (2003). On current strategies for hardware acceleration of digital image restoration filters. WSEAS Transactions on Electronics, 1(3), 551-557. Unavailable

Granger, E., Savaria, Y., & Lavoie, P. (2003). A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. IEEE Transactions on Pattern Analysis and Machine Intelligence, 25(4), 524-528. External link

Ghattas, H., Mbaye, M. M., Pepga, J. B., & Savaria, Y. (2003, January). SoC platform architecture for a network processor [Paper]. International Symposium on System-on-Chip, Tampere, Finland. External link

Granger, É., Savaria, Y., & Lavoie, P. (2002). A pattern reordering approach based on ambiguity detection for on-line category learning. (Technical Report n° EPM-RT-2001-02). Available

Gagnon, Y., Meunier, M., & Savaria, Y. (2001). Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source. (Patent no. US6329272). External link

Granger, É., Savaria, Y., Lavoie, P., & Cantin, M. A. (1998). Comparison of Self-Organizing Neural Networks for Fast Clustering of Radar Pulses. Signal Processing, 64(3), 249-269. External link

Gagnon, Y., Savaria, Y., Meunier, M., & Thibeault, C. (1997, October). Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model [Paper]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1997), Paris, Fr. External link

Gagnon, Y., Meunier, M., Savaria, Y., & Thibeault, C. (1997, October). Mathematical cost model for redundant multi-processor arrays [Paper]. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. Published in Journal of Microelectronic Systems Integration, 5(4). Unavailable

Granger, É., Savaria, Y., Blaquière, Y., Cantin, M.-A., & Lavoie, P. (1997). A VLSI architecture for fast clustering with fuzzy ART neural networks. Journal of Microelectronic Systems Integration, 5(1), 3-18. Unavailable

Granger, É., Blaquière, Y., Savaria, Y., Cantin, M.-A., & Lavoie, P. (1996, August). VLSI architecture for fast clustering with fuzzy ART neural networks [Paper]. 1st International Workshop on Neural Networks for Identification, Control, Robotics, and Signal/Image Processing (NICROSP 1996), Venice, Italy. External link

Gadiri, A., Savaria, Y., & Kaminska, B. (1995, September). Optimized CMOS compatible photoreceiver [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, QC, Canada. External link

Ghannoum, S., Chtchvyrkov, D., & Savaria, Y. (1994, May). Comparative study of single-phase clocked latches using estimation criteria [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. External link

Ghannoum, S., Chtchvyrkov, D., & Savaria, Y. (1994, August). Single-clock dynamic latches optimization [Paper]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. External link

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Hassan, A., Trigui, A., Savaria, Y., & Sawan, M. (2023, September). High-Temperature Fully Integrated Wireless Monitoring Systems for Aerospace Applications [Paper]. IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE 2023), Aveiro, Portugal. External link

Hassan, A., Noël, J.-P., Savaria, Y., & Sawan, M. (2022). Circuit Techniques in GaN Technology for High-Temperature Environments. Electronics, 11(1), 22 pages. External link

Hoque, M. U., Kumar, D., Audet, Y., & Savaria, Y. (2022). Design and Analysis of a 35 GHz Rectenna System for Wireless Power Transfer to an Unmanned Air Vehicle. Energies, 15(1), 19 pages. External link

Hammoud, A., Assaf, H., Savaria, Y., Nguyen, D. K., & Sawan, M. (2022). A Molecular Imprinted PEDOT CMOS Chip-based Biosensor for Carbamazepine Detection. IEEE Transactions on Biomedical Circuits and Systems, 16(1), 15-23. External link

Hassan, A., Amer, M., Savaria, Y., & Sawan, M. (2020). Fully Integrated Digital GaN-based LSK Demodulator for High-Temperature Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(9), 1579-1583. Available

Henwood, S., Leduc-Primeau, F., & Savaria, Y. (2020, August). Layerwise noise maximisation to train low-energy deep neural networks [Paper]. 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020), Genova, Italy. External link

Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2020). Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. Journal of Electronic Testing-Theory and Applications, 35(6), 823-838. External link

Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2020). Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(3), 764-776. External link

Hassan, A., Amer, M., Savaria, Y., & Sawan, M. (2020, June). Towards GaN500-based high temperature ICs: Characterization and modeling up to 600°C [Paper]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Qc, Canada. External link

Hassan, A., Ali, M., Trigui, A., Savaria, Y., & Sawan, M. (2019). A GaN-based wireless monitoring system for high-temperature applications. Sensors, 19(8), 1785 (17 pages). Available

Hassan, A., Ali, M., Savaria, Y., & Sawan, M. (2019). GaN-based LSK demodulators for wireless data receivers in high-temperature applications. Microelectronics Journal, 84, 129-135. Available

Hoque, K. A., Ait Mohamed, O., & Savaria, Y. (2019). Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs. Reliability Engineering and System Safety, 182, 107-119. External link

Hassan, A., Savaria, Y., & Sawan, M. (2018). Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 2085-2098. Available

Hasib, O. A.-T., Crepeau, D., Awad, T., Dulipovici, A., Savaria, Y., & Thibeault, C. (2018, April). Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits [Paper]. 36th IEEE VLSI Test Symposium (VTS 2018), Los Alamitos, CA (6 pages). External link

Hassan, A., Savaria, Y., & Sawan, M. (2018). GaN Integration Technology, an Ideal Candidate for High-Temperature Applications: A Review. IEEE Access, 6, 78790-78802. External link

Hamad, G. B., Ammar, M., Mohamed, O. A., & Savaria, Y. (2018). New insights into soft-faults induced cardiac pacemakers malfunctions analyzed at system-level via model checking. IEEE Access, 6, 62107-62119. External link

Hamad, G. B., Ammar, M., Mohamed, O. A., & Savaria, Y. (2018, September). System-Level Characterization, Modeling, and Probabilistic Formal Analysis of LEON3 Vulnerability to Transient Faults [Paper]. 18th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2018), Piscataway, NJ, USA (4 pages). External link

Hamad, G. B., Kazma, G., Mohamed, O. A., & Savaria, Y. (2017, July). Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT [Paper]. 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece. External link

Hoque, K. A., Ait Mohamed, O., & Savaria, Y. (2017). Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications. Journal of Applied Logic, 25(47-68), 47-68. External link

Hamad, G. B., Ait Mohamed, O., & Savaria, Y. (2017). Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits. Journal of Electronic Testing: Theory and Applications, 33(5), 607-620. External link

Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2016, September). Investigating the efficiency of cell level hardening techniques of single event transients via SMT [Paper]. 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2016), Bremen, Germany (4 pages). External link

Hoque, F., Savaria, Y., & Cardinal, C. (2017, April). Joint power control and beamformer design with antenna selection [Paper]. 30th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2017), Windsor, ON, Canada. External link

Hassan, A., Ali, M., Trigui, A., Hached, S., Savaria, Y., & Sawan, M. (2017, June). Stability of GaN150-based HEMT in high temperature up to 400C [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link

Hoque, K. A., Mohamed, O. A., & Savaria, Y. (2016, April). Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience [Paper]. Annual IEEE Systems Conference (SysCon 2016), Orlando, Flordia (6 pages). External link

Hussain, W., Fakhoury, H., Desgreys, P., Blaquiere, Y., & Savaria, Y. (2016). An asynchronous delta-modulator based A/D converter for an electronic system prototyping platform. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(6), 751-762. External link

Hussain, W., Savaria, Y., & Blaquiere, Y. (2016, May). A compact spatially configurable differential input stage for a field programmable interconnection network [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. External link

Hamad, G. B., Kazma, G., Mohamed, O. A., & Savaria, Y. (2016, September). Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients [Paper]. Forum on Specification and Design Languages (FDL 2016), Bremen, Germany (7 pages). External link

Hussain, W., Valorge, O., Blaquiere, Y., & Savaria, Y. (2016). A novel spatially configurable differential interface for an electronic system prototyping platform. Integration, the VLSI Journal, 55, 129-137. External link

Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2016, May). Towards formal abstraction, modeling, and analysis of single event transients at RTL [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. External link

Hasib, O. A. T., Savaria, Y., & Thibeault, C. (2016, April). WeSPer: a flexible small delay defect quality metric [Paper]. 34th IEEE VLSI Test Symposium (VTS 2016), Las Vegas, Nevada (6 pages). External link

Hassan, A., Trigui, A., Shafique, U., Savaria, Y., & Sawan, M. (2016, May). Wireless power transfer through metallic barriers enclosing a harsh environment, feasibility and preliminary results [Poster]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. External link

Hamad, G. B., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (2015). Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits. Microelectronics Reliability, 55(1), 238-250. External link

Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2015, July). Efficient Multilevel Formal Analysis and Estimation of Design Vulnerability to Single Event Transients [Paper]. 21st International On-Line Testing Symposium (IOLTS 2015), Athena Pallas, Greece (6 pages). External link

Hussain, W., Blaquiere, Y., & Savaria, Y. (2015). An interface for open-drain bidirectional communication in field programmable interconnection networks. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(10), 2465-2475. External link

Hoque, K. A., Mohamed, O. A., & Savaria, Y. (2015, March). Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2015), Grenoble, France. External link

Hamad, G. B., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (2014, June). Abstracting Single Event Transient characteristics variations due to input patterns and fan-out [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, VIC, Australia (4 pages). External link

Hamad, G. B., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (2014, August). Modeling, analyzing, and abstracting single event transient propagation at gate level [Paper]. IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX, USA. External link

Hoque, K. A., Mohamed, O. A., Savaria, Y., & Thibeault, C. (2014, October). Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications [Paper]. 12th ACM/IEEE International Conference on Methods and Models for System Design (MEMOCODE 2014), Lausanne, Switzerland. External link

Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2014, December). Probabilistic model checking of single event transient propagation at RTL level [Paper]. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France. External link

Hoque, K. A., Ait Mohamed, O., Savaria, Y., & Thibeault, C. (2013, October). Early analysis of soft error effects for aerospace applications using probabilistic model checking [Paper]. 2nd International Workshop of Formal Techniques for Safety-Critical Systems (FTSCS 2013), Queenstown, New Zealand. External link

Hussain, W., Savaria, Y., & Blaquière, Y. (2013, May). An interface for the I2C protocol in the WaferBoard TM [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, Chine. External link

Hamad, G. B., Hasan, S. R., Mohamed, O. A., & Savaria, Y. (2013, September). Investigating the impact of propagation paths and re-convergent paths on the propagation induced pulse broadening [Paper]. 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2013), Oxford, United kingdom (4 pages). External link

Hashemi, S. S., Sawan, M., & Savaria, Y. (2012). A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices. IEEE Transactions on Biomedical Circuits and Systems, 6(4), 326-335. External link

Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2011). All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. Integration, the VLSI Journal, 44(1), 22-38. External link

Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(8), 2020-2031. External link

Hasan, S. R., Belanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10), 2696-707. External link

Hasib, O. A., Sawan, M., & Savaria, Y. (2010, May). Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. External link

Hasan, S. R., Pontikakis, B., & Savaria, Y. (2009, May). An all-digital skew-adaptive clock scheduling algorithm for heterogeneous multiprocessor systems on chips (MPSoCs) [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan. External link

Hashemi, S., Sawan, M., & Savaria, Y. (2009, June). Fully-integrated low-voltage high-efficiency CMOS rectifier for wirelessly powered devices [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link

Hashemi, S., Sawan, M., & Savaria, Y. (2009, December). A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices [Paper]. 16th IEEE International Conference on Electronics, Circuits and Systems, Yasmine Hammamet, Tunisia. External link

Hashemi, S., Sawan, M., & Savaria, Y. (2009). A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results. Microelectronics Journal, 40(11), 1547-1554. External link

Hasan, S. R., Bélanger, N., & Savaria, Y. (2008). All digital skew tolerant synchronous interfacing methods for high-Performance point-to-point communication in DSM SoCs. (Technical Report n° EPM-RT-2008-10). Available

Hasan, S. R., Belanger, N., & Savaria, Y. (2008, October). All-digital skew-tolerant interfacing method for systems with rational frequency ratios among multiple clock domains: leveraging a priori timing information [Paper]. 1st Microsystems and Nanoelectronics Research Conference. External link

Hasan, S. R., & Savaria, Y. (2007, May). Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, USA (4 pages). External link

Hadjiat, K., St-Pierre, F., Bois, G., Savaria, Y., Langevin, M., & Paulin, P. (2007, December). An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco. External link

Hasan, S. R., & Savaria, Y. (2007, August). Metastability tolerant mesochronous synchronization [Paper]. 50th Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montreal, QC, Canada. External link

Hashemi, S., Sawan, M., & Savaria, Y. (2007, December). A novel fully-integrated low-drop voltage cmos rectifier for wirelessly powered devices [Paper]. IEEE International Conference on Microelectronics, Cairo, Egypt. External link

Huang, Z., Savaria, Y., Sawan, M., & Meinga, R. (2006, May). High-voltage operational amplifier based on dual floating-gate transistors [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. External link

Hashemi, S., Sawan, M., & Savaria, Y. (2006, May). A power planning model for implantable stimulators [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. External link

Hashemi, S., Sawan, M., & Savaria, Y. (2005, December). Modeling power budget requirements of implantable electronic devices [Paper]. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2005), Tunisie. External link

Hashemi, S., Sawan, M., & Savaria, Y. (2004, June). Characterization of Stress Induced Defects in Deep Sub-Micron MOSFETS [Paper]. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Hasan, S. R., Landry, A., Savaria, Y., & Nekili, M. (2004, June). Design constraints of hypertransport-compatible networks-on-chip [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Huang, Z., Savaria, Y., & Sawan, M. (2004, June). Robust design of a dynamically controlled low-power level-up shifter operating up to 300V [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Hashemi, S., Sawan, M., & Savaria, Y. (2002, January). Analysis of power chains in transcutaneously powered electronic implants [Paper]. 7th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 2002), Lubljana. Unavailable

Hébert, O., Kraljic, I. C., & Savaria, Y. (2000, May). A method to derive application-specific embedded processing cores [Paper]. 8th International Workshop on Hardware/Software Codesign (CODES 2000), San Diego, CA, USA. External link

Hrytzak, R., Savaria, Y., & Goslin, G. (1997, January). Reconfigurable computing greatly simplifies system development [Paper]. DSP World Spring Design Conference. Unavailable

Haccoun, D., & Savaria, Y. (1990). Étude et réalisation de codeurs et décodeurs à haute vitesse pour codes convolutionnels. (Technical Report n° EPM-RT-90-08). Available

Haccoun, D., Lavoie, P., & Savaria, Y. (1987). New architectures for fast convolutional encoders and threshold decoders. (Technical Report n° EPM-RT-87-46). Available

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Ignat, N., Nicolescu, B., Savaria, Y., & Nicolescu, G. Soft-Error Classification and Impact Analysis on Real-Time Operating Systems [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2006). External link

Izouggaghen, B., Khouas, A., & Savaria, Y. (2004, May). Spurs modeling in direct digital period synthesizers related to phase accumulator truncation [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. External link

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Jin, Z.-F., Yang, M., Savaria, Y., & Wu, K. (2004, July). Analysis of gate modulation in nanoscale field effect transistors using an equivalent substrate integrated waveguide (SIW) model [Paper]. 10th International Symposium on Antenna Technology and Applied Electromagnetics and URSI Conference (ANTEM/URSI 2004), Ottawa, Ont., Canada. External link

Jiang, Y. T., Wang, Y. K., Song, X. Y., & Savaria, Y. (2004). Computation of Signal Output Probability for Boolean Functions Represented by Obdd. Computers & Mathematics With Applications, 47(12), 1865-1874. External link

Jin, Z.-F., Laurin, J.-J., & Savaria, Y. Comparison of Propagation Characteristics Between Single and Coupled Mis Interconnect Topologies in Vlsi Circuits [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). External link

Jin, Z.-F., Laurin, J.-J., & Savaria, Y. (2002). A practical approach to model long MIS interconnects in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(4), 494-507. External link

Jiang, Y., Tang, Y., Wang, Y., & Savaria, Y. (1999, January). Evaluating the ouptput probability of boolean functions without floating point operations [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 1999), Edmonton. External link

Jin, Z.-F., Laurin, J.-J., & Savaria, Y. New approach to analyze interconnect delays in RC wire models [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1999). Unavailable

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Kern, J., Henwood, S., Mordido, G., Dupraz, E., Aissa-El-Bey, A., Savaria, Y., & Leduc-Primeau, F. (2022, June). MemSE: Fast MSE Prediction for Noisy Memristor-Based DNN Accelerators [Paper]. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) - Intelligent Technology in the Post-Pandemic Era, Incheon, South Korea. External link

Kazma, G., Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2017, May). Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories [Paper]. Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta. External link

Kazma, G., Bany Hamad, G., Ait Mohamed, O., & Savaria, Y. (2017, June). Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link

Khanzadi, H., Savaria, Y., & David, J. P. (2017, June). A data driven CGRA Overlay Architecture with embedded processors [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link

Kazma, G., Hamad, G. B., Mohamed, O. A., & Savaria, Y. (2016, December). Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis [Paper]. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2016), Monte Carlo, Monaco. External link

Khelifi, M., Massicotte, D., & Savaria, Y. (2016, May). Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. External link

Khanzadi, H., Savaria, Y., & David, J. P. (2015, June). Mapping applications on two-level configurable hardware [Paper]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec (8 pages). External link

Khelifi, M., Massicotte, D., & Savaria, Y. (2015, October). Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems [Paper]. 1st IEEE Nordic Circuits and Systems Conference (NORCAS 2015), Oslo, Norway (4 pages). External link

Keklikian, T., Langlois, J. M. P., & Savaria, Y. (2014, June). A Memory Transaction Model for Sparse Matrix-Vector Multiplications on GPUs [Paper]. 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivières, Canada. External link

Kowarzyk, G., Belanger, N., Haccoun, D., & Savaria, Y. (2014). Optimizing the parallel tree-search for finding shortest-span error-correcting CDO codes. IEEE Transactions on Parallel and Distributed Systems, 25(11), 2992-3001. External link

Kowarzyk, G., Belanger, N., Haccoun, D., & Savaria, Y. (2013). Efficient parallel search algorithm for determining optimal R=1/2 systematic convolutional self-doubly orthogonal codes. IEEE Transactions on Communications, 61(3), 865-876. External link

Kowarzyk, G., Belanger, N., Haccoun, D., & Savaria, Y. (2012). Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Transactions on Communications, 60(1), 3-8. External link

Kowarzyk, G., Bélanger, N., & Savaria, Y. (2011, December). A GPGPU-based software implementation of the PBDI deinterlacing algorithm [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link

Kowarzyk, G., Savaria, Y., & Haccoun, D. (2008, May). Searching for short-span convolutional doubly self-orthogonal codes: a parallel implicitly-exhaustive-search algorithm [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2008), Niagara Falls, Ontario. External link

Khali, H., Savaria, Y., & Houle, J.-L. (2005). A system level implementation strategy and partitioning algorithm for applications based on lookup tables. International Journal of Computer and Electrical Engineering, 31(7), 485-502. External link

Khali, H., & Savaria, Y. (2003, December). Hardware-software co design model for real-time 3D image computation using active laser range finders : a case study [Paper]. 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2003), Sharjah, United Arab Emirates. External link

Khali, H., Savaria, Y., Houle, J. L., Rioux, M., Beraldin, J. A., & Poussart, D. (2003). Improvement of Sensor Accuracy in the Case of a Variable Surface Reflectance Gradient for Active Laser Range Finders. IEEE Transactions on Instrumentation and Measurement, 52(6), 1799-1808. External link

Khali, H., Savaria, Y., & Houle, J.-L. (1997, July). Computational limits of homogeneous acceleration using lookup tables [Paper]. 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada. Unavailable

Kafrounni, M., Thibeault, C., & Savaria, Y. (1997, January). Cost model for VLSI/MCM systems [Paper]. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France. External link

Kermouche, R., Audet, D., & Savaria, Y. (1995). On the optimization of integrated hierarchical bus architectures to achieve efficient fault-tolerance. Journal of Microelectronic Systems Integration, 3(1), 47-63. Unavailable

Khali, H., Savaria, Y., Houle, J.-L., Beraldin, J. A., Blais, F., & Rioux, M. (1995, September). VLSI chip for 3-D camera calibration [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, Québec. External link

Kermouche, R., & Savaria, Y. (1994, October). Defect and fault tolerant scan chains [Paper]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1994), Montréal, Québec. External link

Kermouche, R., Savaria, Y., & Audet, D. (1994, January). Harvest model of an integrated hierarchical-bus architecture [Paper]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA. External link

Kroumba, S. M., Bois, G., & Savaria, Y. (1994, August). Synthesis approach for the generation of parallel architectures [Paper]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. External link

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Luinaud, T., Langlois, J. M. P., & Savaria, Y. (2022). Symbolic analysis for data plane programs specialization. ACM Transactions on Architecture and Code Optimization, 20(1), 1-21. External link

Luinaud, T., Santiago da Silva, J., Langlois, J. M. P., & Savaria, Y. (2021, February). Design Principles for Packet Deparsers on FPGAs [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) (7 pages). Available

Luinaud, T., Stimpfling, T., Santiago da Silva, J., Savaria, Y., & Langlois, J. M. P. (2020, May). Bridging the gap: FPGAs as programmable switches [Paper]. 21st IEEE International Conference on High Performance Switching and Routing (HPSR 2020) (7 pages). External link

Laparra, G., Li, M., Zhu, G., & Savaria, Y. (2020). Desynchronized Model Predictive Control for Large Populations of Fans in Server Racks of Datacenters. IEEE Transactions on Smart Grid, 11(1), 411-419. External link

Luinaud, T., Stimpfling, T., Santiago Da Silva, J., Savaria, Y., & Langlois, J. M. P. (2020, February). Unleashing the Power of FPGAs as Programmable Switches [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, CA, USA (1 page). External link

Leonardon, M., Cassagne, A., Leroux, C., Jego, C., Hamelin, L.-P., & Savaria, Y. (2019). Fast and Flexible Software Polar List Decoders. Journal of Signal Processing Systems for Signal Image and Video Technology, 91(8), 937-952. External link

Léonardon, M., Leroux, C., Binet, D., Langlois, J. M. P., Jégo, C., & Savaria, Y. (2018, May). Custom low power processor for polar decoding [Paper]. IEEE International Symposium on Circuits & Systems (ISCAS 2018), Florence, Italy. External link

Laflamme-Mayer, N., Kowarzyk, G., Blaquiere, Y., Savaria, Y., & Sawan, M. (2018). A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(2), 304-315. External link

Li, M., Chen, C., Zhu, G., & Savaria, Y. (2018, August). Local Queueing-Based Data-Driven Task Scheduling for Multicore Systems [Paper]. 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada. External link

Lepercq, É., Blaquière, Y., & Savaria, Y. (2018). A pattern-based routing algorithm for a novel electronic system prototyping platform. Integration, 62, 224-237. External link

Leonardon, M., Leroux, C., Jaaskelainen, P., Jego, C., & Savaria, Y. (2018, December). Transport Triggered Polar Decoders [Paper]. 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing (ISTC 2018), Hong Kong (5 pages). External link

Li, M., Zhu, G., Savaria, Y., & Lauer, M. (2017). Reliability Enhancement of Redundancy Management in AFDX Networks. IEEE Transactions on Industrial Informatics, 13(5), 2118-2129. Available

Luinaud, T., Savaria, Y., & Langlois, J. M. P. (2017, May). An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search [Paper]. Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta. External link

Luinaud, T., Savaria, Y., & Langlois, J. M. P. (2017, February). An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only) [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, California. External link

Lakhssassi, A., Palenychka, R., Savaria, Y., Sayde, M., & Zaremba, M. (2016). Monitoring thermal stress in wafer-scale integrated circuits by the attentive vision method using an infrared camera. IEEE Transactions on Circuits and Systems for Video Technology, 26(2), 412-424. External link

Laflamme-Mayer, N., Blaquiere, Y., Savaria, Y., & Sawan, M. (2014). A configurable multi-rail power and I/O pad applied to wafer-scale systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(11), 3135-3144. External link

Li, M., Lauer, M., Zhu, G., & Savaria, Y. (2014). Determinism enhancement of AFDX networks via frame insertion and sub-virtual link aggregation. IEEE Transactions on Industrial Informatics, 10(3), 1684-1695. External link

Lakhssassi, A., Palenychka, R., Sayde, M., Savaria, Y., Zaremba, M., & Kengne, E. (2013, September). A spatiotemporal attention operator for monitoring thermo-mechanical stress in wafer-scale integrated circuits using an infrared camera [Paper]. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy. External link

Lepercq, E., Valorege, O., Basile-Bellavance, Y., Laflamme-Mayer, N., Blaquière, Y., & Savaria, Y. (2009, October). An interconnection network for a novel reconfigurable circuit board [Paper]. 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada. External link

Lacourse, A., Ducharme, M., St-Jean, H., Gagnon, Y., Savaria, Y., & Meunier, M. (2009). Tunable semiconductor component provided with a current barrier. (Patent no. US7564078). External link

Lepercq, E., Blaquiere, Y., Norman, R., & Savaria, Y. (2009, May). Workflow for an electronic configurable prototyping system [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan. External link

Lu, Z., El-Fouladi, J., Martel, S., & Savaria, Y. (2008, June). A hybrid bacteria and microparticle detection platform on a CMOS chip: design, simulation and testing considerations [Paper]. 14th IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW 2008) (7 pages). External link

Lu, Z., El-Fouladi, J., Savaria, Y., & Martel, S. (2007, October). A hybrid bacteria and microparticle detection platform on a CMOS chip [Paper]. 11th International Conference on Miniaturized Systems for Chemistry and Life Science, Paris, France. Unavailable

Ling, W., & Savaria, Y. (2005, March). Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations [Paper]. 6th International Symposium on Quality Electronic Design, San Jose, California. External link

Landry, A., Savaria, Y., & Nekili, M. (2005, June). Circuits techniques for a 2 GHz AMBA AHB Bus [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, Canada. External link

Landry, A., Nekili, M., & Savaria, Y. (2005, May). A novel 2 GHz Mulit-layer AMBA high-Speed bus interconnect matrix for SoC platforms [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Japon. External link

Landry, A., Savaria, Y., & Nekili, M. (2004, December). A beyond-1 GHz high-speed bus for SoC DSP platforms [Paper]. 16th International Conference on Microelectronics (ICM 2004), Tunisie. External link

Layachi, M., Savaria, Y., & Rochefort, A. The Effect of Pi-Coupling on the Electronic Properties of 1,4-Dithiol Benzene Stacking [Paper]. International Conference on Mems, Nano and Smart Systems (ICMENS 2004). External link

Lafrance, L.-P., & Savaria, Y. (2004, July). A framework for implementing reusable digital signal processing modules [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link

Ling, W., & Savaria, Y. (2004, July). Variable-precision multiplier for equalizer with adaptive modulation [Paper]. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japon. External link

Loiseau, L., & Savaria, Y. (2003). Design reuse. In System-on-chip for real-time applications (Vol. 711, 29-82). External link

Lu, M., Savaria, Y., Qiu, B., & Taillefer, J. (2003, November). IEEE 1149.1 based defect and fault tolerant scan chain for wafer scale integration [Paper]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states. External link

Lu, M., Savaria, Y., Qiu, B., & Taillefer, J. (2003, November). IEEE 1149.1 based defect and fault tolerant scan chain for water safe integration [Paper]. 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Boston, MA, USA. External link

Lemire, J. F., Aboulhamid, E. M., Savaria, Y., Bois, G., & Baron, A. (2003, January). Implementing e assertion checkers from an SDL executable specifications [Paper]. DVCON, San José, USA. Unavailable

Loiseau, L., & Savaria, Y. (2002, July). Methodologies and Strategies for Effective Design-Reuse [Paper]. System-on-Chip for Real-Time Applications. External link

Lamarche, P. H., & Savaria, Y. (2003, January). VHDL source code generator and analysis tool to design linear interpolars [Paper]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Unavailable

Lafrance, L.-P., Cantin, M.-A., Savaria, Y., Sung, S. H., & Lavoie, P. (2002, May). Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. External link

Loiseau, L., & Savaria, Y. (2002). Methodologies and Strategies for Effective Design Reuse. Canadian Journal of Electrical and Computer Engineering, 27(4), 165-169. Unavailable

Le Chapelain, B., Mechain, A., Savaria, Y., & Bois, G. (1999, May). Development of a high performance TSPC library for implementation of large digital building blocks [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. External link

Lavoie, P., Crespo, J. F., & Savaria, Y. (1999). Generalization, Discrimination, and Multiple Categorization Using Adaptive Resonance Theory. IEEE Transactions on Neural Networks, 10(4), 757-767. External link

Lavoie, P., Crespo, J. F., & Savaria, Y. (1997, June). Multiple categorization using fuzzy ART [Paper]. IEEE International Conference on Neural Networks (ICNN 1997), Houston, TX, USA. External link

Lejmi, S., Bois, G., & Savaria, Y. (1996, January). On the effects of retiming applied to self-checking sequential circuit [Paper]. 2nd IEEE On-Line Testing Workshop, Biarritz. Unavailable

Lavoie, P., Crespo, J.-F., & Savaria, Y. (1996, January). On the stability of Fuzzy ART [Paper]. 18th Biennal Symposium on Communications, Kingston. Unavailable

Lavoie, P., Haccoun, D., & Savaria, Y. (1994). Systolic architecture for fast stack sequential decoders. IEEE Transactions on Communications, 42(2/3/4, pt.), 324-335. External link

Lavoie, P., Haccoun, D., & Savaria, Y. (1988). Spécification d'un décodeur séquentiel rapide utilisant une queue prioritaire systolique. (Technical Report n° EPM-RT-88-11). Available

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Mohammadi, H. M., Edrisi, M. H., & Savaria, Y. (2023). Enhanced Artificial Vision for Visually Impaired Using Visual Implants. IEEE Access, 11, 80020-80029. Available

Mashreghi-Moghadam, P., Ould-Bachir, T., & Savaria, Y. An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs [Paper]. 2023 IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, CA, USA (5 pages). External link

Mafi, H., Ali, M., Savaria, Y., Honarparvar, M., & Ben-Hamida, N. (2023, June). Background Calibration of Time-Interleaved ADCs with Polyphase Filters [Paper]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). External link

Makhroute, E.-M., Elharti, M.-A., Brouillard, V., Savaria, Y., & Ould-Bachir, T. (2023, December). Implementing and Evaluating a P4-based Access Gateway Function on a Tofino Switch [Paper]. 6th International Conference on Advanced Communication Technologies and Networking (CommNet 2023), Rabat, Morocco (7 pages). External link

Mashreghi-Moghadam, P., Ould-Bachir, T., & Savaria, Y. (2022, May). A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. External link

Meng, L., Zhu, G., & Savaria, Y. (2018, May). Delay bound analysis for heterogeneous multicore systems using network calculus [Paper]. 13th IEEE Conference on Industrial Electronics and Applications (ICIEA 2018), Wuhan, China. External link

Mohajertehrani, M., Savaria, Y., & Sawan, M. (2018). Harvesting energy from aviation data lines: implementation and experimental results. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(6), 2048-2057. External link

Mohajertehrani, M., Shafique, U., Savaria, Y., & Sawan, M. (2015, December). Harvesting energy from data lines for avionics applications: power conversion chain architecture [Paper]. 27th International Conference on Microelectronics (ICM 2015), Casablanca, Maroc. External link

Mirzadeh, Z., Boland, J.-F., & Savaria, Y. (2015, May). Modeling the faulty behaviour of digital designs using a feed forward neural network approach [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal. External link

Mahvash Mohammadi, H., Savaria, Y., & Langlois, J. M. P. (2012). Enhanced motion compensated deinterlacing algorithm. IET Image Processing, 6(8), 1041-1048. External link

Mbaye, M. M., Belanger, N., Savaria, Y., & Pierre, S. (2012). Loop Acceleration Exploration for ASIP Architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), 684-696. External link

Mohammadi, H. M., Savaria, Y., & Langlois, J. M. P. (2011). Hybrid video deinterlacing algorithm exploiting reverse motion estimation. IET Image Processing, 5(7), 611-618. External link

Marche, D., & Savaria, Y. (2010). Modeling R-2R segmented-ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(1), 31-43. External link

Marche, D., Savaria, Y., & Gagnon, Y. (2009). An improved switch compensation technique for inverted R-2R Ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(6), 1115-1124. External link

Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (2009). Performance characterization for the implementation of content addressable memories based on parallel hashing memories. In Transactions on High-Performance Embedded Architectures and Compilers. II (Vol. 5470, 307-325). External link

Marche, D., Savaria, Y., & Gagnon, Y. (2008). Laser Fine-Tuneable Deep-Submicrometer Cmos 14-Bit Dac. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(8), 2157-2165. External link

Mbaye, M., Belanger, N., Savaria, Y., & Pierre, S. (2008, July). Loop-oriented metrics for exploring an application-specific architecture design-space [Paper]. International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2008). External link

Mohammadi, H. M., Langlois, J. M. P., & Savaria, Y. (2007). A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Transactions on Consumer Electronics, 53(3), 1117-1124. External link

Mbaye, M. M., Belanger, N., Savaria, Y., & Pierre, S. (2007). A Novel Application-Specific Instruction-Set Processor Design Approach for Video Processing Acceleration. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 47(3), 297-315. External link

Meunier, M., Gagnon, Y., Lacourse, A., Ducharme, M., Rioux, S., & Savaria, Y. (2007, May). Precision resistor laser trimming for analog microelectronics [Paper]. Photonic Applications Systems Technologies Conference, Baltimore, Maryland, USA. External link

Mbaye, M., Lebel, D., Belanger, N., Savaria, Y., & Pierre, S. (2006, May). Design exploration with an application-specific instruction-set processor for ELA deinterlacing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. External link

Mahvash, M. H., Savaria, Y., & Langlois, J. M. P. (2006, June). Real-time ELA de-interlacing with the Xtensa reconfigurable processor [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link

Mohammadi, H. M., Langlois, J. M. P., & Savaria, Y. (2006, December). A threshold-based deinterlacing algorithm using motion compensation and directional interpolation [Paper]. 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France. External link

Morin, D., Savaria, Y., & Sawan, M. (2005, June). A 200 MSPS 10-bit pipelined ADC using digital calibration [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec City, Que., Canada. External link

Mbaye, M., Bélanger, N., Savaria, Y., & Pierre, S. (2005, May). Application Specific Instruction-Set Processor Generation for Video Processing Based on Loop Optimization [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link

Marche, D., Savaria, Y., & Gagnon, Y. (2005, May). A New Switch Compensation Technique for Inverted R-2r Ladder Dacs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link

Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (2005, June). Parallel hashing memories : an alternative to content addressable memories [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec City, Que., Canada. External link

Morin, D., Normandin, F., Grandmaison, M. E., Dang, H., Savaria, Y., & Sawan, M. (2004, July). An intellectual property module for auto-calibration of time-interleaved pipelined analog-to-digital converters [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link

Mbaye, M. M., Tohio, B., Savaria, Y., & Pierre, S. Performance of a Firewire-Ethernet Protocols Conversion on an Arm7 Embedded Processor [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003). External link

Meunier, M., Gagnon, Y., Savaria, Y., & Lacourse, A. (2002, May). Laser tuning silicon microdevices for analogue microelectronics [Paper]. SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging (Opto Canada 2002), Ottawa, ON, Canada. External link

Meunier, M., Gagnon, Y., Savaria, Y., Lacourse, A., & Cadotte, M. (2001, June). A novel laser trimming technique for microelectronics [Paper]. European Materials Research Society 2001-Symposium L "Photon-Induced Surface Processing", Strasbourg, France. Published in Applied Surface Science, 186(1-4). External link

Meunier, M., Gagnon, Y., Savaria, Y., Lacourse, A., & Cadotte, M. A novel laser trimming technique for microelectronics [Paper]. 6th Conference on Laser Applications in Microelectronic and Optoelectronic Manufacturing (LAMOM 2001). External link

Monte, G., Antaki, B., Patenaude, S., Savaria, Y., Thibeault, C., & Trouborst, P. (2001, April). Tools for the characterization of bipolar CML testability [Paper]. 19th IEEE VLSI Test Symposium (VTS 2001), Marina Del Rey, CA, USA. External link

Marriott, P., Kraljic, I., & Savaria, Y. (1998, January). Parallel ultra large scale engine SIMD architectures for real time digital signal processing applications [Paper]. International Conference on Computer Design (ICCD 1998), Austin. External link

N

Noghabaei, S. M., Radin, R. L., Savaria, Y., & Sawan, M. (2022). A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(1), 440-451. External link

Noghabaei, S. M., Radin, R. L., Savaria, Y., & Sawan, M. (2018, May). A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (4 pages). External link

Nsame, P., Bois, G., & Savaria, Y. (2015, May). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platforms [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal. External link

Nsame, P., Bois, G., & Savaria, Y. (2014, August). Adaptive real-time DSP acceleration for SoC applications [Paper]. 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX. External link

Nsame, P., Bois, G., & Savaria, Y. (2014, December). A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT [Paper]. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France. External link

Nsame, P., Bois, G., & Savaria, Y. (2014, May). Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications [Paper]. IEEE 23rd North Atlantic Test Workshop (NATW 2014), Johnson City, NY, USA (4 pages). External link

Nguyen, H. H., Guillemot, M., Savaria, Y., & Blaquiere, Y. (2012, October). A new approach for pin detection for an electronic system prototyping reconfigurable platform [Paper]. 23rd IEEE International Symposium on Rapid System Prototyping (RSP 2012), Tampere, Finland. External link

Nishi, R., Zhu, G., & Savaria, Y. (2012, April). Optimal scheduling policy for AFDX end-systems with virtual links of identical bandwidth allocation gap size [Paper]. 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2012), Montréal, Québec. External link

Nourivand, A., Al-Khalili, A. J., & Savaria, Y. (2012). Postsilicon Tuning of Standby Supply Voltage in Srams to Reduce Yield Losses Due to Parametric Data-Retention Failures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(1), 29-41. External link

Nourivand, A., Al-Khalili, A. J., & Savaria, Y. (2011). Analysis of resistive open defects in drowsy SRAM cells. Journal of Electronic Testing: Theory and Applications, 27(2), 203-213. External link

Naderi, A., Sawan, M., & Savaria, Y. (2009). Undersampling delta-sigma modulators : theory, design and implementation. External link

Naderi, A., Sawan, M., & Savaria, Y. (2009). A low-power 2 GHz data conversion using delta modulation for portable application. Integration, the VLSI Journal, 42(1), 68-76. External link

Norman, R., Valorge, O., Blaquière, Y., Lepercq, É., Basile-Bellavance, Y., El-Alaoui, Y., Prytula, R., & Savaria, Y. (2008, June). An active reconfigurable circuit board [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, QC, Canada. External link

Nourivand, A., Al-Khalili, A. J., & Savaria, Y. (2008, August). Aggressive leakage reduction of SRAMs using error checking and correcting (ECC) techniques [Paper]. 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2008), Knoxville, TN, United states. External link

Norman, R., Lepercq, E., Blaquiere, Y., Valorge, O., Basile-Bellavance, Y., Prytula, R., & Savaria, Y. (2008, June). An interconnection network for a novel reconfigurable circuit board [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link

Ngoyi, G.-A. B., Langlois, J. M. P., & Savaria, Y. (2008, June). Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link

Naderi, A., Sawan, M., & Savaria, Y. (2008). On the design of undersampling continuous-time bandpass delta - Sigma modulators for gigahertz frequency A/D conversion. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(11), 3488-3499. External link

Naderi, A., Sawan, M., & Savaria, Y. (2007, August). A 1.8GHz CMOS continuous-time band-pass delta-sigma modulator for RF receivers [Paper]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montréal, Québec. External link

Nicolescu, B., Ignat, N., Savaria, Y., & Nicolescu, G. (2006). Analysis of real-time systems sensitivity to transient faults using MicroC kernel. IEEE Transactions on Nuclear Science, 53(4), 1902-1909. External link

Naderi, A., Sawan, M., & Savaria, Y. (2006, May). Design of an active-RC bandpass filter for a subsampling RF delta modulator [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2006), Ottawa, ON, Canada. External link

Naderi, A., Sawan, M., & Savaria, Y. (2006, May). A novel 2-GHz band-pass delta modulator dedicated to wireless receivers [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. External link

Naderi, A. H., Sawan, M., & Savaria, Y. (2005, June). A 1-mW 2-GHz Q-enhanced LC bandpass filter for low-power RF applications [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005). External link

Nicolescu, B., Gorse, N., Savaria, Y., Aboulhamid, E. M., & Velazco, R. (2005). On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach. IEEE Transactions on Nuclear Science, 52(5), 1555-1561. External link

Nicolescu, B., Ignat, N., Savaria, Y., & Nicolescu, G. (2005, September). Sensitivity of real-time operating systems to transient faults : A cause study for microC kernel [Paper]. 8th European Conference on Radiation and its Effects on Components and Systems (RADECS 2005). External link

Nsame, P., & Savaria, Y. (2004, July). A customizable embedded SoC platform architecture [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link

Nsame, P., & Savaria, Y. (2004, September). Multi-processor SoC integration: a case study on BlueGene [Paper]. IEEE International SOC Conference (SOCC 2004). External link

Nicolescu, B., Savaria, Y., & Velazco, R. (2004, July). Performance evaluation and failure rate prediction for the soft implemented error detection technique [Paper]. 10th IEEE International On-Line Testing Symposium, Funchal, Madeira Island, Portugal. External link

Nicolescu, B., Savaria, Y., & Velazco, R. (2004). Software detection mechanisms providing full coverage against single bit-flip faults. IEEE Transactions on Nuclear Science, 51(6), 3510-3518. External link

Nicolescu, B., Gorse, N., Savaria, Y., Aboulhamid, E. M., & Velazco, R. (2004, September). Validating a dynamic signature monitoring approach using the LTL model checking technique [Paper]. Workshop on Radiation Effects on Components and Systems (RADECS 2004), Madrid, Espagne. Unavailable

Nicolescu, B., Perronnard, P., Velazco, R., & Savaria, Y. (2003, November). Efficiency of transient bit-flips detection by software means a complete study [Paper]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Cambridge, MA, USA. External link

Nicolescu, B., Savaria, Y., & Velazco, R. (2003, November). SIED: software implemented error detection [Paper]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states. External link

Nsame, P., & Savaria, Y. (2003, January). System-level design closure [Paper]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Unavailable

Nekili, M., Savaria, Y., & Bois, G. (2001, May). Minimizing process-induced skew using elay tuning [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie. External link

Nsame, P., Grou-Szabo, R., & Savaria, Y. (2000, January). INTIME: a multi-tool specification environment for ensuring timing constraints integrity for SOC design [Paper]. IP Based Design 2000, Grenoble, France. External link

Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. External link

Nsame, P., & Savaria, Y. (1999, January). Virtualising on-chip bus interfaces for improved embedded processor system performance [Paper]. IFIP International Workshop on IP Based Synthesis and System Design, Grenoble, France. Unavailable

Nekili, M., Savaria, Y., Bois, G., Bayoumi, M. A., & Jullien, G. (1998, February). Design of clock distribution networks in presence of process variations [Paper]. 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA. External link

Nekili, M., Bois, G., & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. External link

Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Technical Report n° EPM-RT-94-09). Restricted access

Nekili, M., Savaria, Y., & Bois, G. (1994, January). Fast low-power driver for long interconnections in VLSI systems [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), Londres. External link

Nekili, M., Savaria, Y., & Bois, G. (1994, August). A variable-size parallel regenerator for long integrated interconnections [Paper]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. External link

Nekili, M., & Savaria, Y. (1992, May). Optimal methods of driving interconnections in VLSI circuits [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. External link

O

Oukaira, A., Touati, D. E., Hassan, A., Ali, M., Savaria, Y., & Lakhssassi, A. (2022, October). FEM-based Thermal Profile Prediction for Thermal Management of System-on-Chips [Paper]. 8th International Conference on Optimization and Applications (ICOA 2022), Genoa, Italy (4 pages). External link

Oukaira, A., Hassan, A., Ali, M., Savaria, Y., & Lakhssassi, A. (2022). Towards real-time monitoring of thermal peaks in systems-on-chip (SoC). Sensors, 22(15), 5904 (12 pages). External link

Oukaira, A., Touati, D. E., Hassan, A., Ali, M., Savaria, Y., & Lakhssassi, A. (2021, August). Thermo-mechanical Analysis and Fatigue Life Prediction for Integrated Circuits (ICs) [Paper]. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2021), Lansing, MI, USA. External link

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Posso, J., Bois, G., & Savaria, Y. (2022, May). Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. External link

Pal, N., Kilaru, A., Savaria, Y., & Lakhssassi, A. (2017, June). Hybrid features of tamura texture and shape-based image retrieval [Paper]. 5th International Conference on Advanced Computing, Networking, and Informatics (ICACNI 2017), Goa, India. External link

Pal, N., Kilaru, A., Savaria, Y., & Lakhssassi, A. (2018, July). Thermal image processing to Recognize and Quantify Pain in Human Body [Paper]. International Conference on Smart Computing and Electronic Enterprise (ICSCEE 2018), Shah Alam, Malaysia (5 pages). External link

Prieur, D., Granger, E., Savaria, Y., & Thibeault, C. (2016). Efficient identification of faces in video streams using low-power multi-core devices. In Handbook of pattern recognition and computer vision (5th ed.). External link

Pons, J.-F., Brault, J.-J., & Savaria, Y. (2013). Modeling, design and implementation of a low-power FPGA based asynchronous wake-up receiver for wireless applications. Analog Integrated Circuits and Signal Processing, 77(2), 169-182. Available

Pons, J.-F., Brault, J.-J., & Savaria, Y. (2012, June). An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks [Paper]. 10th IEEE International New Circuits and Systems Conference (NEWCAS 2012), Montréal, Québec. External link

Pons, J.-F., Brault, J.-J., & Savaria, Y. (2012, August). State-holding free NULL Convention Logic [Paper]. 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012), Boise, ID, United states. External link

Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (2008, June). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link

Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (2007, May). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana. External link

Pontikakis, B., Boyer, F.-R., Savaria, Y., & Bui, H. T. (2007, August). Precise free-running period synthesizer (FRPS) with process and temperature compensation [Paper]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). External link

Pontikakis, B., Boyer, F.-R., & Savaria, Y. (2006, May). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. External link

Provost, G., Cantin, M. A., Sawan, M., Cardinal, C., Savaria, Y., & Haccoun, D. (2005, May). Fast parameters optimization of an iterative decoder using a configurable hardware accelerator [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japon. External link

Pontikakis, B., Boyer, F.-R., & Savaria, Y. (2005, July). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period [Paper]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. External link

Peterson, K., & Savaria, Y. (2004, May). Assertion-based on-line verification and debug environment for complex hardware systems [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. External link

Planque, F., Kraljic, I., & Savaria, Y. (2000, September). Mapping irregular algorithms in a custom computing image processing framework [Paper]. 3rd Annual Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD 2000), Laurel, Maryland. Unavailable

Poiré, P., Cantin, M.-A., Daniel, H., Blaquière, Y., Savaria, Y., Pocek, K. L., & Arnold, J. M. (1998, April). A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing [Paper]. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA. External link

Poiré, P., Savaria, Y., Daniel, H., Cantin, M. A., & Blaquière, Y. (1998, November). Hardware/software codesign of a Fuzzy ART neural clusterer : The benefits of configurable computing [Paper]. 3rd Conference on Configurable Computing, Boston MA, USA. External link

Pera, F., Savaria, Y., & Bois, G. (1997, June). Time delay measurement methods for integrated transmission lines and high speed cells characterization [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong. External link

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Qavamy, Z., Ghavami, B., Nabavi, M., & Savaria, Y. (2021, August). Non-parametric Statistical Static Timing Analysis based on Improved Parallel Monte Carlo [Paper]. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2021), Lansing, Michigan. External link

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Robache, R., Boland, J.-F., Thibeault, C., & Savaria, Y. (2013, June). A methodology for system-level fault injection based on gate-level faulty behavior [Paper]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. External link

Rioux, S., Lacourse, A., Ducharme, M., Gagnon, Y., Savaria, Y., & Meunier, M. (2005, May). Design methods for CMOS low-current finely tunable voltage references covering a wide output range [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Japon. External link

Robert, M., Savaria, Y., & Wang, C. (2004, June). Analysis of metrics used to compare analog-to-digital converters [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Richard, J.-F., & Savaria, Y. (2004, June). High voltage charge pump using standard CMOS technology [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link

Regimbal, S., Savaria, Y., & Bois, G. (2004, July). Verification strategy determination using dependence analysis of transaction-level models [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link

Regimbal, S., Lemire, J. F., Savaria, Y., Bois, G., Aboulhamid, M., & Baron, A. (2002, July). Aspect Partitioning for Hardware Verification Reuse [Paper]. System-on-Chip for Real-Time Applications. External link

Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E. M., & Baron, A. (2003, June). Automating functional coverage analysis based on an executable specification [Paper]. 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications. External link

Renaud, M., & Savaria, Y. (2003, May). A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2003). External link

Richard, J. F., Lessard, B., Meingan, R., Martel, S., & Savaria, Y. (2003, January). High voltage interfaces for CMOS/DMOS technologies [Paper]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Unavailable

Renaud, M., & Savaria, Y. (2002, May). A linear phase detector for arbitrary clock signals [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix-Scottsdale, AZ. External link

Rzeszut, J., Kaminska, B., & Savaria, Y. (1995, November). New method for testing mixed analog and digital circuits [Paper]. 4th Asian Test Symposium, Bangalore, India. External link

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Su, M., David, J. P., Savaria, Y., Pontikakis, B., & Luinaud, T. (2022, May). An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. External link

Salehi, M., Ali, M., Savaria, Y., & Sawan, M. (2020, November). A 58 nW 35 ppm/C oscillator for iot battery-less sensor applications [Paper]. 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2020), Glasgow, UK (4 pages). External link

Samadani, S. M., Savaria, Y., & Nerguizian, C. (2020, May). Indoor localization using channel state information with regression artificial neural networks [Paper]. 91st IEEE Vehicular Technology Conference (VTC 2020), Antwerp, Belgium (4 pages). External link

Saeidi, R., Nabavi, M., & Savaria, Y. (2020, August). SRAM Security and Vulnerability to Hardware Trojan: Design Considerations [Paper]. 63rd IEEE International Midwest Symposium on Circuits and Systems, (MWSCAS 2020), Springfield, MA, USA. External link

Stimpfling, T., Belanger, N., Langlois, J. M. P., & Savaria, Y. (2019). SHIP: a scalable high-performance IPv6 lookup algorithm that exploits prefix characteristics. IEEE/ACM Transactions on Networking, 27(4), 1529-1542. External link

Stimpfling, T., Langlois, J. M. P., Bélanger, N., & Savaria, Y. (2018, May). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis [Paper]. 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.. External link

Stimpfling, T., Bélanger, N., Cherkaoui, O., Béliveau, A., Béliveau, L., & Savaria, Y. (2017). Extensions to decision-tree based packet classification algorithms to address new classification paradigms. Computer Networks, 122, 83-95. External link

Siaka, F., Akbarniai Tehrani, M., Laurin, J.-J., & Savaria, Y. (2017). Radar system with enhanced angular resolution based on a novel frequency scanning reflector antenna. IET Radar, Sonar & Navigation, 11(2), 350-358. External link

Sarbishei, I., Vakili, S., Langlois, J. M. P., & Savaria, Y. (2017, May). Scalable memory-less architecture for string matching with FPGAs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD. External link

Sion, G., Blaquiere, Y., & Savaria, Y. (2015, July). Defect diagnosis algorithms for a field programmable interconnect network embedded in a very large area integrated circuit [Paper]. 21st International On-Line Testing Symposium (IOLTS 2015), Athena Pallas, Greece. External link

Shaheen, M. A., Hamoui, A. A., & Savaria, Y. (2014, June). A current-output DAC for low-power low-noise log-domain modulators [Paper]. 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivieres, QC, Canada. External link

Shaheen, M. A., Savaria, Y., & Hamoui, A. A. (2014). Design and modeling of high-resolution multibit log-domain modulators. Analog Integrated Circuits and Signal Processing, 79(3), 569-582. External link

Stimpfling, T., Savaria, Y., Beliveau, A., Belanger, N., & Cherkaoui, O. (2013, June). Optimal packet classification applicable to the OpenFlow context [Paper]. 1st ACM Workshop on High Performance and Programmable Networking (HPPN 2013), New York, NY, United states. External link

Singh, R., Audet, Y., Gagnon, Y., Savaria, Y., Boulais, E., & Meunier, M. (2011). A laser-trimmed rail-to-rail precision CMOS operational amplifier. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), 75-79. External link

Sahraii, N., Savaria, Y., Thibeault, C., & Gagnon, F. (2008, June). Scheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link

Salomon, M.-É., Izouggaghen, B., Khouas, A., & Savaria, Y. (2008). Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. IEEE Transactions on Instrumentation and Measurement, 57(10), 2320-2328. External link

Singh, R., Audet, Y., Gagnon, Y., & Savaria, Y. (2007, May). Integrated circuit trimming technique for offset reduction in a precision CMOS amplifier [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, USA. External link

Saheb, J.-F., Richard, J.-F., Sawan, M., Meingan, R., & Savaria, Y. (2007). System integration of high voltage electrostatic MEMS actuators. Analog Integrated Circuits and Signal Processing, 53(1), 27-34. External link

Sawan, M., Harvey, J.-F., Roy, M., Coulombe, J., Savaria, Y., & Donfack, C. (2006). Body electronic implant and artificial vision system thereof. (Patent no. US7027874). External link

Salomon, M. E., Khouas, A., & Savaria, Y. (2005, May). A Complete Spurs Distribution Model for Direct Digital Period Synthesizers [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link

Sawan, M., Djemouai, A., El-Sankary, K., Dang, H., Naderi, A., Savaria, Y., & Gagnon, F. (2005, June). High speed ADCs dedicated for wideband wireless receivers [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, QC, Canada. External link

Saheb, J. F., Richard, J.-F., Meingan, R., Sawan, M., & Savaria, Y. (2005, June). System integration of high voltage electrostatic MEMS Actuators [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, Canada. External link

Savaria, Y., El Hassan, F., Khali, H., & Sawan, M. (1998, January). Effective hardware/software implementation of a viterbi decoder using an FPGA-based reconfigurable computing platform [Paper]. FDP 1998. Unavailable

Savaria, Y. (1998). Study of neural networks for clustering radar signals: Final report. (Technical Report n° 98-610). Unavailable

Savaria, Y., Bois, G., Popovic, P., & Wayne, A. Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems [Paper]. High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic. External link

St-Amand, R., Sawan, M., & Savaria, Y. (1996). Design and optimization of a low DC offset CMOS current-source dedicated to implantable miniaturized stimulators. Analog Integrated Circuits and Signal Processing, 11(1), 47-61. External link

Soufi, M., Rochon, S., Savaria, Y., & Kaminska, B. (1996, April). Design and performance of CMOS TSPC cells for high speed pseudo random testing [Paper]. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link

Savaria, Y., Thibeault, C., & Ivanov, A. (1996). IEEE VSLI test symposium - meeting the quality challenge. IEEE Design & Test of Computers, 13(3), 110-112. Unavailable

Sawan, M., St-Amand, R., & Savaria, Y. (1995, December). Design and optimization of programmable biphasic current-sources [Paper]. 2nd annual International Conference on Electronics, Circuits and Systems (ICECS 1995), Amman, Jordan. Unavailable

Soufi, M., Savaria, Y., & Kaminska, B. (1995, April). On the design of at-speed testable VLSI circuits [Paper]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link

Soufi, M., Savaria, Y., & Kaminska, B. (1995, April). On Using partial reset for pseudo-random testing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA. External link

Soufi, M., Savaria, Y., Darlay, F., & Kaminska, B. (1995). Producing reliable initialization and test of sequential circuits with pseudorandom vectors. IEEE Transactions on Computers, 44(10), 1251-1256. External link

St-Amand, R., Savaria, Y., & Sawan, M. (1994, August). Design optimization of a current source for microstimulator applications [Paper]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. External link

Savaria, Y., Chtchvyrkov, D., & Currie, J. F. (1994, May). Fast CMOS voltage-controlled ring oscillator [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. External link

St.-Amand, R., Sawan, M., & Savaria, Y. (1994, November). Generation of balanced bipolar stimuli based on current sources without coupling capacitor [Paper]. 16th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 1994), Baltimore, MD, USA. External link

Savaria, Y. (1994). Parallel microprocessor architecture. (Patent no. US5276893). External link

Soufi, M., Savaria, Y., Kaminska, B., & Darlay, F. (1994). Producing reliable initialization and test of sequential circuits with pseudo-random vectors. (Technical Report n° EPM-RT-94-23). Restricted access

Savaria, Y. (1988). Conception et vérification des circuits VLSI. Unavailable

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Touati, D. E., Oukaira, A., Hassan, A., Ali, M., Lakhssassi, A., & Savaria, Y. (2023). Accurate On-Chip Thermal Peak Detection Based on Heuristic Algorithms and Embedded Temperature Sensors. Electronics, 12(13), 18 pages. Available

Taghizadeh, R. G., Marvasti, M. B., Asghari, S. A., Taghizadeh, R. G., Nabavi, M., & Savaria, Y. (2021). IBU: An In-block Update Address Mapping Scheme for Solid-state Drives. IEEE Access, 10, 4934-4947. External link

Trigui, A., Ali, M., Hached, S., David, J. P., Ammari, A. C., Savaria, Y., & Sawan, M. (2020). Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(11), 3978-3990. External link

Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (2019). Energy Efficient Generic Demodulator for High Data Transmission Rate Over an Inductive Link for Implantable Devices. IEEE Access, 7, 159379-159389. External link

Trigui, A., Hached, S., Ammari, A., Savaria, Y., & Sawan, M. (2019). Maximizing Data Transmission Rate for Implantable Devices Over a Single Inductive Link: Methodological Review. IEEE Reviews in Biomedical Engineering, 12, 72-87. External link

Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (2018). A 1.5-pJ/bit, 9.04-Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer. IEEE Transactions on Circuits and Systems II: Express Briefs, 65(10), 1420-1424. External link

Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (2017, June). A 14.5 W generic carrier width demodulator for telemetry-based medical devices [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link

Tazi, F. Z., Thibeault, C., & Savaria, Y. (2016, May). Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA [Paper]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2016), Vancouver, British Columbia (5 pages). External link

Tehrani, M. A., Savaria, Y., & Laurin, J.-J. (2016). Multiple targets direction-of-arrival estimation in frequency scanning array antennas. IET Radar, Sonar and Navigation, 10(3), 624-631. External link

Trigui, A., Ali, M., Ammari, A. C., Savaria, Y., & Sawan, M. (2016, June). Quad-Level Carrier Width Modulation demodulator for micro-implants [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). External link

Tazi, F. Z., Thibeault, C., Savaria, Y., Pichette, S., & Audet, Y. (2014). On extra delays affecting I/O blocks of an SRAM-based FPGA due to ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3138-3145. External link

Trabelsi, A., & Savaria, Y. (2013, June). A 2D Gaussian smoothing kernel mapped to heterogeneous platforms [Paper]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. External link

Tehrani, M. A., Laurin, J.-J., & Savaria, Y. (2013, April). Angular superresolution algorithm for frequency scanning array antennas [Paper]. IEEE Radar Conference (RadarCon 2013), Ottawa, ON, Canada. External link

Tremblay, J. P., Savaria, Y., Zhu, G., Ghibeault, C., & Bouanen, S. (2013, October). A hardware prototype for integration, test and validation of avionic networks [Paper]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. External link

Thibeault, C., Hariri, Y., Hasan, S. R., Hobeika, C., Savaria, Y., Audet, Y., & Tazi, F. Z. (2013). A library-based early soft error sensitivity analysis technique for SRAM-based FPGA design. Journal of Electronic Testing: Theory and Applications, 29(4), 457-471. External link

Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2012). Real-time dual-microphone speech enhancement. In Ramakrishnan, S. (ed.), Speech Enhancement, Modeling and Recognition - Algorithms and Applications (19-34). Available

Trentin, D., Savaria, Y., Zhu, G., & Thibeault, C. (2012, October). An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization [Paper]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ. Published in SAE International Journal of Aerospace, 5(1). External link

Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquiere, Y., Moupfouma, F., & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65. External link

Tremblay, J.-P., Savaria, Y., Zhu, G., Thibeault, C., & Bouanen, S. (2012, October). A System Architecture for Smart Sensors Integration in Avionics Applications [Paper]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ. Published in SAE International Journal of Aerospace, 5(1). External link

Tawk, M., Zhu, G., Liu, X., Jian, L., Savaria, Y., & Hu, F. (2011, October). Optimal scheduling and delay analysis for AFDX end-systems [Paper]. SAE AeroTech Congress and Exhibition (AEROTECH 2011), Toulouse, France. External link

Tawk, M., Zhu, G., Savaria, Y., Liu, X., Li, J., & Hu, F. (2011, October). A tight end-to-end delay bound and scheduling optimization of an avionics AFDX network [Paper]. 30th Digital Avionics Systems Conference (DASC 2011), Seattle, WA, United states. External link

Tanguay, L.-F., Savaria, Y., & Sawan, M. (2010, June). A 640 µW frequency synthesizer dedicated to implantable medical microsystems in 90-nm CMOS [Paper]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. External link

Tanguay, L.-F., Sawan, M., & Savaria, Y. (2009). A very-high output impedance charge pump for low-voltage low-power PLLs. Microelectronics Journal, 40(6), 1026-1031. External link

Tremblay, J.-P., Savaria, Y., Thibeault, C., & Mbaye, M. (2008, October). Improving resource utilization in an multiple asynchronous ALU DSP architecture [Paper]. 1st Microsystems and Nanoelectronics Research Conference. External link

Tanguay, L. F., Sawan, M., & Savaria, Y. (2008, November). A very-high output impedance current mirror for very-low voltage biomedical analog circuits [Paper]. IEEE Asia-Pacific Conference on Circuits and Systems, Macao, China. External link

Trabelisi, A., Boyer, F.-R., Savaria, Y., & Boukadoum, M. (2007, August). Improving LPC Analysis of Speech in Additive Noise [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. External link

Trabelisi, A., Boyer, F.-R., Savaria, Y., & Boukadoum, M. (2007, December). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis [Paper]. 14h IEEE International Conference on Electronics, Circuits & Systems, Marrakech, Morocco. External link

Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2007, August). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise [Paper]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). External link

Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise. (Technical Report n° EPM-RT-2006-09). Available

Tanguay, B., Savaria, Y., & Sawan, M. (2004, December). Accelerating equalization algorithms using the Xtensa configurable processor [Paper]. 16th International Conference on Microelectronics (ICM 2004), Tunisie. External link

Tohio, B., Pierre, S., Savaria, Y., & Mbaye, M. M. (2004, May). Protocol convertibility in network processing environments [Paper]. 6th WSEAS International Conference on Telecommunications and Informatics (TELE-INFO 2004), Cancun, Mexico. Published in WSEAS Transactions on Communications, 3(1). Unavailable

Trabelsi, A., Savaria, Y., & Audet, Y. (2003, January). Automatic offset correction technique based on active load tuning [Paper]. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Québec. Unavailable

Tang, Y., Qian, L., Wang, Y., & Savaria, Y. (2003, January). New memory reference reduction method for FFT implementation on DSP [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand. External link

Tohio, B., Pierre, S., Savaria, Y., & Mbaye, M. M. (2003, May). Protocol Convertibility in a Network Processing Environment [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), Montréal, Québec. External link

Thériault, L., Audet, D., & Savaria, Y. (2001, May). Performance estimators for hardware/software co-design [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie. External link

Thibeault, C., Savaria, Y., & Houle, J.-L. (1995). Equivalence proofs of some yield modeling methods for defect-tolerant integrated-circuits. IEEE Transactions on Computers, 44(5), 724-728. External link

Thibeault, C., Savaria, Y., & Houle, J.-L. (1994). A fast method to evaluate the optimum number of spares in defect-tolerant integrated-circuits. IEEE Transactions on Computers, 43(6), 687-697. External link

Thibeault, C., Savaria, Y., & Houle, J.-L. (1992). Test quality of hierarchical defect-tolerant integrated circuits. Journal of Electronic Testing, 3(1), 93-102. External link

Thibeault, C., & Savaria, Y. (1992, November). Comparing results from defect-tolerant yield models [Paper]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1992), Dallas, TX, United states. External link

Thibeault, C., Savaria, Y., & Houle, J.-L. (1990). Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits. (Technical Report n° EPM-RT-90-11). Restricted access

Thibeault, C., Savaria, Y., & Houle, J.-L. (1988). Yield formula for two-level hierarchical fault-tolerant integrated circuit. (Technical Report n° EPM-RT-88-25). Restricted access

V

Vakili, S., Langlois, J. M. P., Savaria, Y., & Manjikian, N. (2018). Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Communications, 12(7), 868-875. External link

Vakili, S., Langlois, J. M. P., Boughzala, B., & Savaria, Y. (2016, March). Memory-efficient string matching for intrusion detection systems using a high-precision pattern grouping algorithm [Paper]. 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California. External link

Vakili, S., Gil, D. C., Langlois, J. M. P., Savaria, Y., & Bois, G. (2011, December). Customized embedded processor design for global photographic tone mapping [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link

Valorge, O., André, W., Savaria, Y., & Blaquière, Y. (2011, June). Power supply analysis of a large area integrated circuit [Paper]. 9th IEEE International New Circuits and Systems Conference (NEWCAS 2011), Bordeaux, France. External link

Valorge, O., Blaquiere, Y., & Savaria, Y. (2010, December). A spatially reconfigurable fast differential interface for a wafer scale configurable platform [Paper]. 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010), Athens, Greece. External link

Valorge, O., Nguyen, A. T., Blaquière, Y., Norman, R., & Savaria, Y. (2008, August). Digital signal propagation on a wafer-scale smart active programmable interconnect [Paper]. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), St. Julian's, Malta. External link

Valorge, O., Marche, D., Lacourse, A., Sawan, M., & Savaria, Y. (2007, December). Signal Integrity Analysis of a High Precision D/A Converter [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco. External link

Vado, P., Savaria, Y., Zoccarato, Y., & Robach, C. (2000, May). A methodology for validating digital circuits with mutation testing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland. External link

Vinh, H. T., Audet, D., & Savaria, Y. (1993, September). Performance models for optimizing a hierarchical-bus multiprocessor architecture [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 1993), Vancouver, BC, Canada. External link

W

Wu, Y., Ding, Y., Ding, S., Savaria, Y., & Li, M. (2021). Autonomous Last-Mile Delivery Based on the Cooperation of Multiple Heterogeneous Unmanned Ground Vehicles. Mathematical Problems in Engineering, 2021, 1-15. External link

Wang, J., Zeng, Y., Wei, S., Wei, Z., Wu, Q., & Savaria, Y. (2021). Multi-Sensor Track-to-Track Association and Spatial Registration Algorithm under Incomplete Measurements. IEEE Transactions on Signal Processing, 69, 3337-3350. External link

Wu, Y., Li, M., Li, G., & Savaria, Y. (2021). Persistence region monitor with a pheromone-inspired robot swarm sensor network. IEEE Internet of Things Journal, 9(14), 12093-12110. External link

Wolff, B., Fradj, B., Belanger, N., & Savaria, Y. (2018, August). Extending a CPU Cache for Efficient IPv6 Lookup [Paper]. 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada. External link

Wild, G., Savaria, Y., & Meunier, M. (2005, May). Characterization of Laser-Induced Photoexcitation Effect on a Surrounding CMOS Ring Oscillator [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link

Y

Yang, K., Li, M., Zhu, G., & Savaria, Y. (2017). A DAQM-Based Load Balancing Scheme for High Performance Computing Platforms. IEEE Access, 5, 22504-22513. Available

Z

Zhang, Y., Savaria, Y., Zhao, S., Mordido, G., Sawan, M., & Leduc-Primeau, F. (2022, July). Tiny CNN for Seizure Prediction in Wearable Biomedical Devices [Paper]. 44th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2022), Glasgow, United Kingdom. External link

Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (2015). Design intelligence for interconnection realization in power-managed SoCs. In Computational Intelligence in Digital and Network Designs and Applications (69-96). External link

Zarrabi, H., Al-Khalili, A., & Savaria, Y. (2014, December). Vt-conscious repeater insertion in power-managed VLSI [Paper]. International Symposium on Integrated Circuits (ISIC 2014), Singapore. External link

Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (2011, December). Activity management in battery-powered embedded systems: A case study of ZigBee® WSN [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link

Zarrabi, H., Al-Khalili, A., & Savaria, Y. (2011, May). Repeater insertion in power-managed VLSI systems [Paper]. 21st Great Lakes Symposium on VLSI (GLSVLSI 2011), Lausanne, Switzerland. External link

Zarrabi, H., Zilic, Z., Savaria, Y., & Al-Khalili, J. A. (2010). On the Efficient Design & Synthesis of Differential Clock Distribution Networks. In Wang, Z. (ed.), VLSI (331-352). Available

Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (2010, May). An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. External link

Zarreabi, H., Al-Khalili, A. J., & Savaria, Y. (2009, December). Estimation of energy performance in computing platforms [Paper]. 16th IEEE International Conference on Electronics, Circuits and Systems, Yasmine Hammamet, Tunisia. External link

Zarrabi, H., Al-Khalili, A. J., & Savaria, Y. (2009, May). An interconnect-aware delay model for dynamic voltage scaling in nm technologies [Paper]. 19th ACM Great Lakes Symposium on VLSI, Boston, MA, United states. External link

Zarrabi, H., Zilic, Z., Al-Khalili, A. J., & Savaria, Y. (2007, August). A methodology for parallel synthesis of zero skew differential clock distribution networks [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montreal, QC, Canada. External link

Zhengrong, H., Savaria, Y., & Sawan, M. (2004, July). A dynamically controlled and refreshed low-power level-up shifter [Paper]. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japon. External link

List generated on: Mon Feb 26 08:04:31 2024 EST