Nacer-Eddine Belabbes, Alexandre J. Guterman, Yvon Savaria
and Michel Dagenais
Article (1996)
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| Additional Information: | Nom historique du département: Département de génie électrique et de génie informatique |
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| Department: |
Department of Electrical Engineering Department of Computer Engineering and Software Engineering |
| PolyPublie URL: | https://publications.polymtl.ca/31524/ |
| Journal Title: | IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications (vol. 43, no. 2) |
| Publisher: | IEEE |
| DOI: | 10.1109/81.486436 |
| Official URL: | https://doi.org/10.1109/81.486436 |
| Date Deposited: | 18 Apr 2023 15:24 |
| Last Modified: | 25 Sep 2024 16:13 |
| Cite in APA 7: | Belabbes, N.-E., Guterman, A. J., Savaria, Y., & Dagenais, M. (1996). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(2), 143-152. https://doi.org/10.1109/81.486436 |
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