HPQ: a high capacity hybrid priority queue architecture for high-speed network switches

Imad Benacer, François-Raymond Boyer and Yvon Savaria

Paper (2018)

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Department:	Department of Computer Engineering and Software Engineering Department of Electrical Engineering
Research Center:	GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL:	https://publications.polymtl.ca/42429/
Conference Title:	16th IEEE International New Circuits and Systems Conference (NEWCAS 2018)
Conference Location:	Montréal, Québec
Conference Date(s):	2018-06-24 - 2018-06-27
Publisher:	IEEE
DOI:	10.1109/newcas.2018.8585434
Official URL:	https://doi.org/10.1109/newcas.2018.8585434
Date Deposited:	18 Apr 2023 15:02
Last Modified:	25 Sep 2024 16:28

Cite in APA 7:	Benacer, I., Boyer, F.-R., & Savaria, Y. (2018, June). HPQ: a high capacity hybrid priority queue architecture for high-speed network switches [Paper]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. https://doi.org/10.1109/newcas.2018.8585434
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