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François-Raymond BoyerDépartement de génie informatique et génie logiciel
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Alizadeh, R., Belanger, N., Savaria, Y., & Boyer, F.-R. (juin 2016). Performance characterization of an SCMA decoder [Communication écrite]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). HPQS: A fast, high-capacity, hybrid priority queuing system for high-speed networking devices. IEEE Access, 7, 130672-130684. Disponible
Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). A high-speed, scalable, and programmable traffic manager architecture for flow-based networking. IEEE Access, 7, 2231-2243. Disponible
Benacer, I., Boyer, F.-R., & Savaria, Y. (mai 2018). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952. Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (juin 2018). HPQ: a high capacity hybrid priority queue architecture for high-speed network switches [Communication écrite]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. Lien externe
Benacer, I., Boyer, F.-R., & Savaria, Y. (juin 2017). A high-speed traffic manager architecture for flow-based networking [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Benacer, I., Boyer, F.-R., Bélanger, N., & Savaria, Y. (juin 2016). A fast systolic priority queue architecture for a flow-based Traffic Manager [Communication écrite]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Lien externe
Boyer, F.-R., Epassa, H. G., & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290. Lien externe
Benny, O., Rondonneau, M., Chevalier, J., Bois, G., Aboulhamid, E. M., & Boyer, F.-R. (mars 2004). SoC software refinement approach for a systemC platform [Communication écrite]. Design & Verification Conference & Exhibition (DVCon 2004), San Jose, California. Non disponible
Boyer, F.-R., Epassa, H. G., Pontikakis, B., Savaria, Y., & Ling, W. (juin 2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Boyer, F.-R., Yang, L., Aboulamid, E. M., Charest, L., & Nicolescu, G. (décembre 2003). Multiple SimpleScalar Processors with Introspection, under SystemC [Communication écrite]. 46th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2003), Cairo, Egypt. Lien externe
Boyer, F.-R., Aboulhamid, E. M., & Savaria, Y. (août 2001). Minimizing sensitivity to clock skew variations using level sensitive latches [Communication écrite]. 15th European Conference on Circuit Theory and Design (ECCTD 2001), Espoo, Finland. Non disponible
Boyer, F.-R., Aboulhamid, E. M., Savaria, Y., & Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), 516-532. Lien externe
Boyer, F.-R., Aboulhamid, E. M., & Savaria, Y. (janvier 2000). Efficient verification method for a class of multi-phase sequential circuits [Communication écrite]. 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000). Lien externe
Boyer, F.-R., Abiylhamid, E. M., Savaria, Y., & Bennour, I. E. (octobre 1998). Optical design of synchronous circuits using software pipeling techniques [Communication écrite]. VLSI in Computers and Processors, Austin, TX, USA. Lien externe
Chevalier, J., Benny, O., Rondonneau, E. M., Bois, G., & Boyer, F.-R. (2004). SPACE : a hardware/software system C modeling platform including and RTOS. Dans Languages for System Specification : Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems, and Property Specification from FDL'03 (p. 91-104). Lien externe
Cloutier, J., Cosatto, E., Pigeon, S., Boyer, F.-R., & Simard, G. (février 1996). VIP: an FPGA-based processor for image processing and neural networks [Communication écrite]. 5th International Conference on Microelectronics for Neural Networks, Lausanne, Switzerland. Lien externe
Epassa, H. G., Boyer, F.-R., & Savaria, Y. (mai 2005). Implementation of a Cycle by Cycle Variable Speed Processor [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. Lien externe
Hosseini, P., Martins, S., Martin, T., Radziszewski, P., & Boyer, F.-R. (2011). Acoustic emissions simulation of tumbling mills using charge dynamics. Minerals Engineering, 24(13), 1440-1447. Lien externe
Lacroix, A. B., Langlois, J. M. P., Boyer, F.-R., Gosselin, A., & Bois, G. (mars 2016). Node configuration for the Aho-Corasick algorithm in intrusion detection systems [Affiche]. ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, Californie (2 pages). Disponible
Lapalme, J., Aboulhamed, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (juin 2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation [Communication écrite]. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C.. Publié dans ACM Sigplan Notices, 39(7). Lien externe
Lapalme, J., Aboulhamid, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (février 2004). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France. Lien externe
Li, J., Boyer, F.-R., & Aboulhamid, E. M. (juillet 2002). Retargetable C Compiler for Network Processors [Communication écrite]. 6th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida. Non disponible
Martins, S., Hosseini, P., Martin, T., Radziszewski, P., Boyer, F.-R., Faucher, A., Makni, S., & Sabih, A. (septembre 2001). Simulating tumbling mill acoustic signals using DEM [Communication écrite]. 5th International Conference on Autogenous and Semiautogenous Grinding Technology (SAG 2011), Vancouver, B.C.. Non disponible
Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (juin 2013). Design of low power 4-bit flash ADC based on standard cells [Communication écrite]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France (4 pages). Lien externe
Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (mai 2010). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS) [Communication écrite]. IEEE International Symposium on Circuits and Systems. ISCAS 2010, Paris, France. Lien externe
Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (juin 2009). Design and optimization of a low complexity all-digital digital-to-analog converter [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (juin 2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (mai 2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana. Lien externe
Pontikakis, B., Boyer, F.-R., Savaria, Y., & Bui, H. T. (août 2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation [Communication écrite]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). Lien externe
Pontikakis, B., Boyer, F.-R., & Savaria, Y. (mai 2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. Lien externe
Pontikakis, B., Boyer, F.-R., & Savaria, Y. (juillet 2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period [Communication écrite]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. Lien externe
Santiago Da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (avril 2019). Module-per-object: A human-driven methodology for c++-based high-level synthesis design [Communication écrite]. 27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2019), San Diego, CA, United states. Lien externe
Santiago da Silva, J., Boyer, F.-R., Chiquette, L.-O., & Langlois, J. M. P. (juin 2018). Extern objects in P4: an ROHC compressing scheme case study [Communication écrite]. IEEE Conference on Network Softwarization (NetSoft 2018), Montréal, Québec. Lien externe
Santiago da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (février 2018). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA. Lien externe
Siadjine Njinowa, M., Tien Bui, H., & Boyer, F.-R. (2012). Novel Threshold-Based Standard-Cell Flash ADC. Circuits and Systems, 3(1), 29-34. Lien externe
Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2012). Real-time dual-microphone speech enhancement. Dans Ramakrishnan, S. (édit.), Speech Enhancement, Modeling and Recognition - Algorithms and Applications (p. 19-34). Disponible
Trabelsi, A., Boyer, F.-R., & Boukadoum, M. (décembre 2009). Robust Estimation of LP Parameters in White Noise with Unknown Variance [Communication écrite]. 16th IEEE International Conference on Electronics, Circuits and Systems, Medina, Tunisia. Lien externe
Trabelsi, A., Boyer, F.-R., Savaria, Y., & Boukadoum, M. (août 2007). Improving LPC Analysis of Speech in Additive Noise [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. Lien externe
Trabelsi, A., Boyer, F.-R., Savaria, Y., & Boukadoum, M. (décembre 2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis [Communication écrite]. 14h IEEE International Conference on Electronics, Circuits & Systems, Marrakech, Morocco. Lien externe
Trabelsi, A., Boyer, F.-R., & Savaria, Y. (août 2007). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise [Communication écrite]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). Lien externe
Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise. (Rapport technique n° EPM-RT-2006-09). Disponible
Vezant, B., Mansuy, C., Bui, H. T., & Boyer, F.-R. (juin 2009). Direct digital synthesis-based all-digital phase-locked loop [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
