Embedded power-aware cycle by cycle variable speed processor

François-Raymond Boyer, H. G. Epassa and Yvon Savaria

Article (2006)

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Additional Information:	Nom historique du département: Département de génie informatique
Department:	Department of Electrical Engineering Department of Computer Engineering and Software Engineering
PolyPublie URL:	https://publications.polymtl.ca/23315/
Journal Title:	IEE Proceedings. Computers and Digital Techniques (vol. 153, no. 4)
Publisher:	IET
DOI:	10.1049/ip-cdt:20050170
Official URL:	https://doi.org/10.1049/ip-cdt%3a20050170
Date Deposited:	18 Apr 2023 15:17
Last Modified:	08 Apr 2025 02:11

Cite in APA 7:	Boyer, F.-R., Epassa, H. G., & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290. https://doi.org/10.1049/ip-cdt%3a20050170
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