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P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs

Jeferson Santiago da Silva, François-Raymond Boyer and J. M. Pierre Langlois

Paper (2018)

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Department: Department of Computer Engineering and Software Engineering
Research Center: GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL: https://publications.polymtl.ca/39943/
Conference Title: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018)
Conference Location: Monterey, California, USA
Conference Date(s): 2018-02-25 - 2018-02-27
Publisher: ACM
DOI: 10.1145/3174243.3174270
Official URL: https://doi.org/10.1145/3174243.3174270
Date Deposited: 18 Apr 2023 15:03
Last Modified: 05 Apr 2024 11:35
Cite in APA 7: Santiago da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (2018, February). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA. https://doi.org/10.1145/3174243.3174270

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