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J. M. Pierre LangloisDépartement de génie informatique et génie logiciel
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Ahmadi, M., Vakili, S., & Langlois, J. M. P. (2021). CARLA: A Convolution Accelerator with a Reconfigurable and Low-Energy Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(8), 3184-3196. Lien externe
Ahmadi, M., Vakili, S., & Langlois, J. M. P. (juin 2020). An energy-efficient accelerator architecture with serial accumulation dataflow for deep CNNs [Communication écrite]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Québec. Lien externe
Ahmadi, M., Vakili, S., & Langlois, J. M. P. (juin 2020). Heterogeneous distributed SRAM configuration for energy-efficient deep CNN accelerators [Communication écrite]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Québec. Lien externe
Abdelsalam, A. M., Elsheikh, A., Chidambaram, S., David, J. P., & Langlois, J. M. P. (2020). POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. Journal of Signal Processing Systems, 92(1), 95-107. Lien externe
Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (octobre 2019). POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests [Communication écrite]. 13th Conference on Design and Architectures for Signal and Image Processing (DASIP 2019), Montréal, Qc, Canada. Lien externe
Abdelsalam, A. M., Boulet, F., Demers, G., Langlois, J. M. P., & Cheriet, F. (décembre 2018). An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs [Communication écrite]. International Conference on ReConFigurable Computing and FPGAs (ReConFig 2018), Cancun, Mexico (6 pages). Lien externe
Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (octobre 2018). POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal. Lien externe
Ahmadi, M., Vakili, S., Langlois, J. M. P., & Gross, W. J. (juin 2018). Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy [Communication écrite]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. Lien externe
Abdelsalam, A. M., Langlois, J. M. P., & Cheriet, F. (février 2017). Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only) [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, CA, USA. Lien externe
Abdelsalam, A. M., Langlois, J. M. P., & Cheriet, F. (avril 2017). A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation [Communication écrite]. 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2017), Napa, California. Lien externe
Aubertin, P., Langlois, J. M. P., & Savaria, Y. (2012). Real-time computation of local neighborhood functions in application-specific instruction-set processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(11), 2031-2043. Lien externe
Athow, J. L., Rozon, C., Al-Khalili, D., & Langlois, J. M. P. (décembre 2011). A CNFET-based characterization framework for digital circuits [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Allaire, F. C. J., Langlois, J. M. P., Labonté, G., & Tarbouchi, M. (octobre 2010). Two-tiered resolution real-time path evaluation [Communication écrite]. International Conference on Evolutionary Computation, Valencia, Spain. Lien externe
Aubertin, P., Mohammadi, H. M., Savaria, Y., & Langlois, J. M. P. (juin 2009). High performance ASIP implementation of PBDI: a new intra-field deinterlacing method [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Al-Khalili, D., & Langlois, J. M. P. (2003). Phase to sine amplitude conversion system and method. (Brevet no US6657573). Lien externe
Bendaoudi, H., Cheriet, F., Manraj, A., Ben Tahar, H., & Langlois, J. M. P. (2018). Flexible architectures for retinal blood vessel segmentation in high-resolution fundus images. Journal of Real-Time Image Processing, 15(1), 31-42. Lien externe
Bendaoudi, H., Cheriet, F., & Langlois, J. M. P. (octobre 2016). Memory efficient multi-scale line detector architecture for retinal blood vessel segmentation [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2016), Rennes, France. Lien externe
Bilodeau, G.-A., Desgent, S., Farah, R., Duss, S., Langlois, J. M. P., & Carmant, L. (2015). Body temperature measurement of an animal by tracking in biomedical experiments. Signal Image and Video Processing, 9(2), 251-259. Lien externe
Bendaoudi, H., Gan, Q., Cheriet, F., Ben Tahar, H., & Langlois, J. M. P. (décembre 2015). A run-length encoding co-processor for retinal image texture analysis [Communication écrite]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Mexico City, Mexico (6 pages). Lien externe
Bendaoudi, H., Cheriet, F., Ben Tahar, H., & Langlois, J. M. P. (octobre 2014). A Scalable Hardware Architecture for Retinal Blood Vessel Detection in High Resolution Fundus Images [Communication écrite]. Conference on Design & Architectures for Signal & Image Processing (DASIP 2014), Madrid, Spain. Lien externe
Bilodeau, G.-A., Torabi, A., Levesque, M., Ouellet, C., Langlois, J. M. P., Lema, P., & Carmant, L. (2012). Body Temperature Estimation of a Moving Subject From Thermographic Images. Machine Vision and Applications, 23(2), 299-311. Lien externe
Bilodeau, G.-A., Ghali, R., Desgent, S., Langlois, J. M. P., Farah, R., St-Onge, P.-L., Duss, S., & Carmant, L. (juin 2011). Where is the rat? Tracking in low contrast thermographic images [Communication écrite]. IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops (CVPRW 2011), Colorado Springs, CO, United states. Lien externe
Bilodeau, G.-A., Levesque, M., Langlois, J. M. P., Lema, P., & Carmant, L. (janvier 2009). Thermographic body temperature measurement using a mean-shift tracker [Communication écrite]. 2nd International Conference on Bio-Inspired Systems and Signal Processing (BIOSIGNALS 2009), Porto, Portugal. Lien externe
Bouyela Ngoyi, G.-A., Langlois, J. M. P., & Savaria, Y. (juin 2008). Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Chidambaram, S., Langlois, J. M. P., & David, J. P. (mars 2020). PoET-BiN : Power Efficient Tiny Binary Neurons [Communication écrite]. 3rd Conference on Machine Learning and Systems (MLSys 2020), Austin, Texas (12 pages). Non disponible
Chidambaram, S., Riviello, A., Langlois, J. M. P., & David, J. P. (octobre 2018). Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal. Lien externe
Daigneault, M.-A., Langlois, J. M. P., & David, J. P. (octobre 2008). Application Specific Instruction set processor specialized for block motion estimation [Communication écrite]. IEEE International Conference on Computer Design (ICCD 2008), Lake Tahoe, CA. Lien externe
Ebrahimi, A., Pullu, V. N., Langlois, J. M. P., & David, J. P. Iterative pruning algorithm for efficient look-up table implementation of binary neural networks [Communication écrite]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). Lien externe
Farah, R., Langlois, J. M. P., & Bilodeau, G.-A. (2016). Computing a rodent's diary. Signal, Image and Video Processing, 10(3), 567-574. Lien externe
Farah, R., Gan, Q., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (2014). A computationally efficient importance sampling tracking algorithm. Machine Vision and Applications, 25(7), 1761-1777. Lien externe
Fasih, M., Langlois, J. M. P., & Cheriet, F. (février 2014). Retinal image quality assessment using generic features [Communication écrite]. SPIE Medical Imaging, San Diego, California, USA. Lien externe
Farah, R., Langlois, J. M. P., & Bilodeau, G.-A. (2013). Catching a rat by its edglets. IEEE Transactions on Image Processing, 22(2), 668-678. Lien externe
Farah, R., Langlois, J. M. P., & Bilodeau, G.-A. (septembre 2011). RAT: Robust animal tracking [Communication écrite]. 9th IEEE International Symposium on Robotic and Sensors Environments (ROSE 2011), Montréal, Québec. Lien externe
Farah, R., Gan, Q., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (décembre 2011). A tracking algorithm suitable for embedded systems implementation [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Fontaine, S., Goyette, S., Langlois, J. M. P., & Bois, G. (octobre 2008). Acceleration of a 3D target tracking algorithm using an application specific instruction set processor [Communication écrite]. IEEE International Conference on Computer Design (ICCD 2008). Lien externe
Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017). Efficient realization of BCD multipliers using FPGAs. International Journal of Reconfigurable Computing, 2017, 1-12. Disponible
Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (avril 2017). Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier [Communication écrite]. 30th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2017), Windsor, ON, Canada (6 pages). Lien externe
Gan, Q., Séoud, L., Ben Tahar, H., & Langlois, J. M. P. (avril 2016). Memory efficient and constant time 2D-recursive spatial averaging filter for embedded implementations [Communication écrite]. Real-Time Image and Video Processing 2016, part of Photonics Europe 2016, Brussels, Belgium. Lien externe
Gan, Q. F., Langlois, J. M. P., & Savaria, Y. (2014). Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations. Journal of Signal Processing Systems for Signal Image and Video Technology, 75(3), 191-202. Lien externe
Gan, Q., Langlois, J. M. P., & Savaria, Y. (2014). A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems. Circuits, Systems & Signal Processing, 33(11), 3591-3602. Lien externe
Gill, D. C., Langlois, J. M. P., & Savaria, Y. (octobre 2013). Accelerating a modified gaussian pyramid with a customized processor [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2013), Cagliari, Italy. Lien externe
Gan, Q., Langlois, J. M. P., & Savaria, Y. (2013). Parallel array histogram architecture for embedded implementations. Electronics Letters, 49(2), 99-101. Lien externe
Gan, Q., Langlois, J. M. P., & Savaria, Y. (août 2013). A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor [Communication écrite]. 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2013), Columbus, OH, USA. Lien externe
Gao, S., Al-Khalili, D., Chabini, N., & Langlois, J. M. P. (2012). Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Computers and Digital Techniques, 6(6), 372-83. Lien externe
Gil, D. C., Farah, R., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (mai 2011). Comparative analysis of contrast enhancement algorithms in surveillance imaging [Communication écrite]. IEEE International Symposium of Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil. Lien externe
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2010). FPGA-based efficient design approaches for large size two's complement squarers. Journal of Signal Processing Systems, 58(1), 3-15. Lien externe
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (juillet 2007). FPGA-based efficient design approach for large-size two's complement squarers [Communication écrite]. IEEE International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec. Lien externe
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007). Optimised Realisations of Large Integer Multipliers and Squarers Using Embedded Blocks. IET Computers and Digital Techniques, 1(1), 9-16. Lien externe
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (septembre 2006). Efficient FPGA-based realization of complex squarer and complex conjugate using embedded mulitpliers [Communication écrite]. IEEE International SOC Conference (SOCC 2006), Austin, TX, USA. Lien externe
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (juin 2006). Efficient realization of large integers multipliers and squarers [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (mars 2006). An optimized design approach for squaring large integers using embedded hardwired multipliers [Communication écrite]. ACS/IEEE International Conference on Computer Systems and Applications. Lien externe
Gilbert, G., & Langlois, J. M. P. (juin 2005). Multipath greedy algorithm for canonical representation of numbers in the double base number system [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, Canada. Lien externe
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (novembre 2005). Optimized multipliers for large unsigned integers [Communication écrite]. NORCHIP Conference, Oulu, Finlande. Lien externe
Hireche, N., Langlois, J. M. P., & Nicolescu, G. (août 2007). A systolic array for sequence comparison based on two logic levels processing element [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. Lien externe
Hireche, N., Langlois, J. M. P., & Nicolescu, G. (mai 2006). Survey of biological high performance computing: Algorithms, implementations and outlook research [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2006), Ottawa, Ontario. Lien externe
Islam, A., Iqbal, U., Langlois, J. M. P., & Noureldin, A. (2010). Implementation methodology of embedded land vehicle positioning using an integrated GPS and multi sensor system. Integrated Computer-Aided Engineering, 17(1), 69-83. Lien externe
Islam, A., Langlois, J. M. P., & Noureldin, A. (juin 2009). A design methodology for the implementation of embedded vehicle navigation systems [Communication écrite]. IEEE International Conference on Electro/Information Technology, Windsor, ON, Canada. Lien externe
Keklikian, T., Langlois, J. M. P., & Savaria, Y. (juin 2014). A Memory Transaction Model for Sparse Matrix-Vector Multiplications on GPUs [Communication écrite]. 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivières, Canada. Lien externe
Kong, M. Y., Langlois, J. M. P., & Al-Khalili, D. (mai 2008). Efficient FPGA implementation of complex multipliers using the logarithmic number system [Communication écrite]. IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, United states. Lien externe
Luinaud, T., Langlois, J. M. P., & Savaria, Y. (2022). Symbolic analysis for data plane programs specialization. ACM Transactions on Architecture and Code Optimization, 20(1), 1-21. Lien externe
Luinaud, T., Santiago da Silva, J., Langlois, J. M. P., & Savaria, Y. (février 2021). Design Principles for Packet Deparsers on FPGAs [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) (7 pages). Disponible
Lévesque, M., Gao, H.Y., Southward, C., Langlois, J. M. P., Léna, C., & Courtemanche, R. (2020). Cerebellar Cortex 4-12 Hz Oscillations and Unit Phase Relation in the Awake Rat. Frontiers in Systems Neuroscience, 14, 475948 (17 pages). Disponible
Luinaud, T., Stimpfling, T., Santiago da Silva, J., Savaria, Y., & Langlois, J. M. P. (mai 2020). Bridging the gap: FPGAs as programmable switches [Communication écrite]. 21st IEEE International Conference on High Performance Switching and Routing (HPSR 2020) (7 pages). Lien externe
Luinaud, T., Stimpfling, T., Santiago Da Silva, J., Savaria, Y., & Langlois, J. M. P. (février 2020). Unleashing the Power of FPGAs as Programmable Switches [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, CA, USA (1 page). Lien externe
Léonardon, M., Leroux, C., Binet, D., Langlois, J. M. P., Jégo, C., & Savaria, Y. (mai 2018). Custom low power processor for polar decoding [Communication écrite]. IEEE International Symposium on Circuits & Systems (ISCAS 2018), Florence, Italy. Lien externe
Lacroix, A. B., Langlois, J. M. P., Boyer, F.-R., Gosselin, A., & Bois, G. (mars 2016). Node configuration for the Aho-Corasick algorithm in intrusion detection systems [Affiche]. ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, Californie (2 pages). Disponible
Luinaud, T., Savaria, Y., & Langlois, J. M. P. (mai 2017). An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search [Communication écrite]. Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta. Lien externe
Luinaud, T., Savaria, Y., & Langlois, J. M. P. (février 2017). An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only) [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, California. Lien externe
Levesque, M., Langlois, J. M. P., Lema, P., Courtemanche, R., Bilodeau, G.-A., & Carmant, L. (2009). Synchronized Gamma Oscillations (30-50 Hz) in the Amygdalo-Hippocampal Network in Relation With Seizure Propagation and Severity. Neurobiology of Disease, 35(2), 209-218. Lien externe
Lévesque, M., Lema, P., Langlois, J. M. P., Courtemanche, R., & Carmant, L. (2008). Local field potential synchrony in the amygdalo-hippocampal network during kainate induced-seizures. Lien externe
Langlois, J. M. P., & Al-Khalili, D. (2006). Carry-free approximate squaring functions with O(n) complexity and O(1) delay. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(5), 374-378. Lien externe
Langlois, J. M. P. (juin 2006). Design and implementation of high sampling rate programmable FIR filters in FPGAs [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Langlois, J. M. P., Al-Khalili, D., & Al-Hertani, H. '. (juin 2004). Carry free, bit parallel approximate squarers with linear complexity and constant delay [Communication écrite]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. Lien externe
Langlois, J. M. P. (mai 2004). Design of linear phase FIR filters using particle swarm optimization [Communication écrite]. 22nd Biennial Symposium on Communications, Kingston, Canada. Non disponible
Langlois, J. M. P., & Al-Khalili, D. (2004). Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis. IEE Proceedings-Circuits, Devices and Systems, 151(6), 519-528. Lien externe
Langlois, J. M. P., & Al-Khalili, D. (septembre 2003). Low power direct digital frequency synthesizers in 0.18 μm CMOS [Communication écrite]. IEEE Custom Integrated Circuits Conference (CICC 2003), San José, CA, USA. Lien externe
Langlois, J. M. P., & Al-Khalili, D. (2003). Novel approach to the design of direct digital frequency synthesizers based on linear interpolation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50(9), 567-578. Lien externe
Langlois, J. M. P. (2003). Novel design approach and architectures for sinusoid output direct digital frequency synthesis [Thèse de doctorat, Royal Military College of Canada]. Lien externe
Langlois, J. M. P., & Al-Khalili, D. (juin 2003). Piecewise continuous linear interpolation of the sine function for direct digital frequency synthesis [Communication écrite]. IEEE MTT-S International Microwave Symposium (IMS 2003), Philadelphia, PA, USA. Lien externe
Liu, Q., Langlois, J. M. P., Al-Khalili, D., Szwarc, V., & Ink, R. (mai 2003). Synthesis of a 12-bit complex mixer for FPGA implementation [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), Montréal, Québec. Lien externe
Langlois, J. M. P., & Al-Khalili, D. (mai 2002). Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Scottsdale, Arizona, USA. Lien externe
Langlois, J. M. P., & Al-Khalili, D. (avril 2002). A low power direct digital frequency synthesizer with 60 dBc spectral purity [Communication écrite]. 12th ACM Great Lakes symposium on VLSI, New York, NY, USA. Lien externe
Langlois, J. M. P., & Al-Khalili, D. (mai 2002). A new approach to the design of low power direct digital frequency synthesizers [Communication écrite]. IEEE International Frequency Control Symposium and PDA Exhibition, New Orleans, USA. Lien externe
Langlois, J. M. P., Al-Khalili, D., & Inkol, R. J. (2002). Polyphase filter approach for high performance, FPGA-based quadrature demodulation. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 32(3), 237-254. Lien externe
Langlois, J. M. P., & Al-Khalili, D. (août 2001). ROM size reduction with low processing cost for direct digital frequency synthesis [Communication écrite]. IEEE Pacific Rim Conference on Communications, Computers and signal Processing (PACRIM 2001), Victoria, Canada. Lien externe
Langlois, J. M. P. (2000). Design and implementation of wide band quadrature demodulators on field programmable gate arrays [Mémoire de maîtrise, Royal Military College of Canada]. Lien externe
Langlois, J. M. P., Al-Khalili, D., & Inkol, R. J. (mai 1999). A high performance, wide bandwidth, low cost FPGA-based quadrature demodulator [Communication écrite]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 1999), Edmonton, Canada. Lien externe
Mosleh, A., Elmi Sola, Y., Zargari, F., Onzon, E., & Langlois, J. M. P. (2018). Explicit ringing removal in image deblurring. IEEE Transactions on Image Processing, 27(2), 580-593. Lien externe
Mosleh, A., Green, P., Onzon, E., Begin, I., & Langlois, J. M. P. (juin 2015). Camera intrinsic blur kernel estimation: A reliable framework [Communication écrite]. IEEE Conference on Computer Vision and Pattern Recognition (CVPR 2015), Boston, MA, United states. Lien externe
Mosleh, A., Langlois, J. M. P., & Green, P. (septembre 2014). Image deconvolution ringing artifact detection and removal via psf frequency analysis [Communication écrite]. 13th European Conference on Computer Vision (ECCV 2014), Zurich, Switzerland. Lien externe
Mahvash Mohammadi, H., Savaria, Y., & Langlois, J. M. P. (2012). Enhanced motion compensated deinterlacing algorithm. IET Image Processing, 6(8), 1041-1048. Lien externe
Mohammadi, H. M., Savaria, Y., & Langlois, J. M. P. (2011). Hybrid video deinterlacing algorithm exploiting reverse motion estimation. IET Image Processing, 5(7), 611-618. Lien externe
Mohammadi, H. M., Langlois, J. M. P., & Savaria, Y. (2007). A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Transactions on Consumer Electronics, 53(3), 1117-1124. Lien externe
Mahvash, M. H., Savaria, Y., & Langlois, J. M. P. (juin 2006). Real-time ELA de-interlacing with the Xtensa reconfigurable processor [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Mohammadi, H. M., Langlois, J. M. P., & Savaria, Y. (décembre 2006). A threshold-based deinterlacing algorithm using motion compensation and directional interpolation [Communication écrite]. 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France. Lien externe
Rajotte, S., Carolina Gil, D., & Langlois, J. M. P. (mai 2011). Combining ISA extensions and subsetting for improved ASIP performance and cost [Communication écrite]. IEEE International Symposium of Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil. Lien externe
Santiago Da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (avril 2019). Module-per-object: A human-driven methodology for c++-based high-level synthesis design [Communication écrite]. 27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2019), San Diego, CA, United states. Lien externe
Stimpfling, T., Belanger, N., Langlois, J. M. P., & Savaria, Y. (2019). SHIP: a scalable high-performance IPv6 lookup algorithm that exploits prefix characteristics. IEEE/ACM Transactions on Networking, 27(4), 1529-1542. Lien externe
Santiago da Silva, J., Boyer, F.-R., Chiquette, L.-O., & Langlois, J. M. P. (juin 2018). Extern objects in P4: an ROHC compressing scheme case study [Communication écrite]. IEEE Conference on Network Softwarization (NetSoft 2018), Montréal, Québec. Lien externe
Stimpfling, T., Langlois, J. M. P., Bélanger, N., & Savaria, Y. (mai 2018). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis [Communication écrite]. 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.. Lien externe
Santiago da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (février 2018). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA. Lien externe
Sarbishei, I., Vakili, S., Langlois, J. M. P., & Savaria, Y. (mai 2017). Scalable memory-less architecture for string matching with FPGAs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD. Lien externe
Séoud, L., Hurtut, T., Chelbi, J., Cheriet, F., & Langlois, J. M. P. (2016). Red lesion detection using dynamic shape features for diabetic retinopathy screening. IEEE Transactions on Medical Imaging, 35(4), 1116-1126. Lien externe
Séoud, L., Faucon, T., Hurtut, T., Chelbi, J., Cheriet, F., & Langlois, J. M. P. (avril 2014). Automatic detection of microaneurysms and haemorrhages in fundus images using dynamic shape features [Communication écrite]. 11th IEEE International Symposium on Biomedical Imaging (ISBI 2014), Beijing, China. Lien externe
Traore, M., Langlois, J. M. P., & David, J. P. (juin 2022). ASIP accelerator for LUT-based neural networks inference [Communication écrite]. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada. Lien externe
Torabi, A., Bilodeau, G.-A., Levesque, M., Langlois, J. M. P., Lema, P., & Carmant, L. (décembre 2008). Measuring an animal body temperature in thermographic video using particle filter tracking [Communication écrite]. 4th International Symposium on Visual Computing (ISVC 2008), Las Vegas, Nevada. Lien externe
Tchoulack, S., Langlois, J. M. P., & Cheriet, F. (juin 2008). A video stream processor for real-time detection and correction of specular reflections in endoscopic images [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. Lien externe
Vaziri, M., Vakili, S., & Langlois, J. M. P. (juillet 2024). Accuracy-Aware Low-Complexity Deep Learning Models for Automatic Modulation Recognition [Communication écrite]. International Conference on Computing, Internet of Things and Microwave Systems (ICCIMS 2024), Gatineau, QC, Canada. Lien externe
Vakili, S., Vaziri, M., Zarei, A., & Langlois, J. M. P. (2024). DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration. ACM Transactions on Reconfigurable Technology and Systems. Lien externe
Vakili, S., Langlois, J. M. P., Savaria, Y., & Manjikian, N. (2018). Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Communications, 12(7), 868-875. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (2016). Accuracy-aware processor customisation for fixed-point arithmetic. IET Computers and Digital Techniques, 10(1), 1-11. Lien externe
Vakili, S., Langlois, J. M. P., Boughzala, B., & Savaria, Y. (mars 2016). Memory-efficient string matching for intrusion detection systems using a high-precision pattern grouping algorithm [Communication écrite]. 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (juin 2015). Designing Customized Microprocessors for Fixed-Point Computation [Communication écrite]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Customised soft processor design: A compromise between architecture description languages and parameterisable processors. IET Computers and Digital Techniques, 7(3), 122-131. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(12), 1853-1865. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (mai 2013). Finite-precision error modeling using affine arithmetic [Communication écrite]. 38th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013), Vancouver, BC, Canada. Lien externe
Vakili, S., Gil, D. C., Langlois, J. M. P., Savaria, Y., & Bois, G. (décembre 2011). Customized embedded processor design for global photographic tone mapping [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Zeghaida, A.-A., Daultani, D., Langlois, J. M. P., & David, J. P. (août 2024). Scalable Low-Complexity Implementation of Constant Matrix Multiplication Circuits [Communication écrite]. IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS 2024), Springfield, MA, USA. Lien externe
