A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis

Thibault Stimpfling, J. M. Pierre Langlois, Normand Bélanger and Yvon Savaria

Paper (2018)

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Department:	Department of Computer Engineering and Software Engineering Department of Electrical Engineering
Research Center:	GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL:	https://publications.polymtl.ca/39972/
Conference Title:	18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018)
Conference Location:	Washington, D.C.
Conference Date(s):	2018-05-01 - 2018-05-04
Publisher:	IEEE
DOI:	10.1109/ccgrid.2018.00067
Official URL:	https://doi.org/10.1109/ccgrid.2018.00067
Date Deposited:	18 Apr 2023 15:03
Last Modified:	05 Apr 2024 11:35

Cite in APA 7:	Stimpfling, T., Langlois, J. M. P., Bélanger, N., & Savaria, Y. (2018, May). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis [Paper]. 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.. https://doi.org/10.1109/ccgrid.2018.00067
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