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The word cloud is a useful tool for identifying trends and main themes in a corpus of texts, thus facilitating the understanding and analysis of content in a visual and intuitive way.
Alizadeh, R., Bélanger, N., Savaria, Y., & Boyer, F.-R. (2016, June). Performance characterization of an SCMA decoder [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). External link
Alizadeh, R., Bélanger, N., Savaria, Y., & Frigon, J.-F. (2015, June). DPDK and MKL; enabling technologies for near deterministic cloud-based signal processing [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link
Abdollahifakhr, H., Bélanger, N., Savaria, Y., & Gagnon, F. (2015, June). Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link
Benacer, I., Boyer, F.-R., Bélanger, N., & Savaria, Y. (2016, June). A fast systolic priority queue architecture for a flow-based Traffic Manager [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). External link
Beucher, N., Bélanger, N., Savaria, Y., & Bois, G. (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), 155-165. External link
Beucher, N., Bélanger, N., Savaria, Y., & Bois, G. (2006, October). Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor [Paper]. IEEE Workshop on Signal Processing Systems Design and Implementation, Banff, AB, Canada. External link
Bélanger, N., & Savaria, Y. (2006, June). On the design of a double precision logarithmic number system arithmetic unit [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Bélanger, N. (1997). Outils et méthodes pour le traitement parallèle de calculs sur des tableaux [Ph.D. thesis, École Polytechnique de Montréal]. Available
Bélanger, N. (1989). Architectures multiprocesseurs de décodeurs séquentiels à pile [Master's thesis, Polytechnique Montréal]. Available
Dubois, M., Savaria, Y., Haccoun, D., & Bélanger, N. (2006). Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders. IEE Proceedings. Circuits, Devices and Systems, 153(3), 207-213. External link
Fradj, B., Wolff, B., Bélanger, N., & Savaria, Y. (2018, May). Implementation of a cache-based IPv6 lookup system with hashing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (4 pages). External link
Hasan, S. R., Bélanger, N., Savaria, Y., & Ahmad, M. O. (2011). All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. Integration, the VLSI Journal, 44(1), 22-38. External link
Hasan, S. R., Bélanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(8), 2020-2031. External link
Hasan, S. R., Bélanger, N., Savaria, Y., & Ahmad, M. O. (2010). Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10), 2696-707. External link
Hasan, S. R., Bélanger, N., & Savaria, Y. (2008). All digital skew tolerant synchronous interfacing methods for high-Performance point-to-point communication in DSM SoCs. (Technical Report n° EPM-RT-2008-10). Available
Hasan, S. R., Bélanger, N., & Savaria, Y. (2008, October). All-digital skew-tolerant interfacing method for systems with rational frequency ratios among multiple clock domains: leveraging a priori timing information [Paper]. 1st Microsystems and Nanoelectronics Research Conference. External link
Kowarzyk, G., Bélanger, N., Haccoun, D., & Savaria, Y. (2014). Optimizing the parallel tree-search for finding shortest-span error-correcting CDO codes. IEEE Transactions on Parallel and Distributed Systems, 25(11), 2992-3001. External link
Kowarzyk, G., Bélanger, N., Haccoun, D., & Savaria, Y. (2013). Efficient parallel search algorithm for determining optimal R=1/2 systematic convolutional self-doubly orthogonal codes. IEEE Transactions on Communications, 61(3), 865-876. External link
Kowarzyk, G., Bélanger, N., Haccoun, D., & Savaria, Y. (2012). Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Transactions on Communications, 60(1), 3-8. External link
Kowarzyk, G., Bélanger, N., & Savaria, Y. (2011, December). A GPGPU-based software implementation of the PBDI deinterlacing algorithm [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link
Mbaye, M. M., Bélanger, N., Savaria, Y., & Pierre, S. (2012). Loop Acceleration Exploration for ASIP Architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), 684-696. External link
Mbaye, M., Bélanger, N., Savaria, Y., & Pierre, S. (2008, July). Loop-oriented metrics for exploring an application-specific architecture design-space [Paper]. International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2008). External link
Mbaye, M. M., Bélanger, N., Savaria, Y., & Pierre, S. (2007). A Novel Application-Specific Instruction-Set Processor Design Approach for Video Processing Acceleration. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 47(3), 297-315. External link
Mbaye, M., Lebel, D., Bélanger, N., Savaria, Y., & Pierre, S. (2006, May). Design exploration with an application-specific instruction-set processor for ELA deinterlacing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece. External link
Mbaye, M., Bélanger, N., Savaria, Y., & Pierre, S. (2005, May). Application Specific Instruction-Set Processor Generation for Video Processing Based on Loop Optimization [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. External link
Stimpfling, T., Langlois, J. M. P., Bélanger, N., & Savaria, Y. (2018, May). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis [Paper]. 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.. External link
Stimpfling, T., Bélanger, N., Cherkaoui, O., Béliveau, A., Béliveau, L., & Savaria, Y. (2017). Extensions to decision-tree based packet classification algorithms to address new classification paradigms. Computer Networks, 122, 83-95. External link
Stimpfling, T., Savaria, Y., Béliveau, A., Bélanger, N., & Cherkaoui, O. (2013, June). Optimal packet classification applicable to the OpenFlow context [Paper]. 1st ACM Workshop on High Performance and Programmable Networking (HPPN 2013), New York, NY, United states. External link
Wolff, B., Fradj, B., Bélanger, N., & Savaria, Y. (2018, August). Extending a CPU Cache for Efficient IPv6 Lookup [Paper]. 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, ON, Canada. External link
