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Loop Acceleration Exploration for ASIP Architecture

Mame Maria Mbaye, Normand Belanger, Yvon Savaria and Samuel Pierre

Article (2012)

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Department: Department of Computer Engineering and Software Engineering
Department of Electrical Engineering
Research Center: GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL: https://publications.polymtl.ca/14988/
Journal Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (vol. 20, no. 4)
Publisher: IEEE
DOI: 10.1109/tvlsi.2011.2107923
Official URL: https://doi.org/10.1109/tvlsi.2011.2107923
Date Deposited: 18 Apr 2023 15:11
Last Modified: 05 May 2023 15:22
Cite in APA 7: Mbaye, M. M., Belanger, N., Savaria, Y., & Pierre, S. (2012). Loop Acceleration Exploration for ASIP Architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), 684-696. https://doi.org/10.1109/tvlsi.2011.2107923

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