All digital skew tolerant synchronous interfacing methods for high-Performance point-to-point communication in DSM SoCs

High-performance clocking of IPs, within a skew budget, is becoming difficult in Deep Sub-Micron technologies. Therefore, the concept of local islands of independent clocks prevails in SoCs, which can communicate using various synchronous and asynchronous interfacing methodologies. However, asynchronous methods are inadequately supported in the context of conventional synchronous design flows, and are also associated with substantial failure rates. By contrast, synchronous interfacing methods often require PLL based synchronization, which requires phase correction that consumes useful bandwidth and mixed signal components. This work proposes a novel and all digital synchronous design method for point-to-point communications, using n interfacing registers and locally delayed clocks with phase adjustments. An overall improvement in skew tolerance of up to n/2 to n times, compared to conventional designs, is obtained depending on the context. This is proven analytically. The modules are assumed to have same or integer multiple frequencies. Gate-level simulations are used to validate the analytical results. A proof of concept implementation of the proposed design is demonstrated using a Virtex-II Pro FPGA from Xilinx.

Mots clés

SoC, Multiple Clock Domains, GALS, Synchronizers, Inter-Module Communication