Nasreddine Hireche, J. M. Pierre Langlois
and Gabriela Nicolescu
Paper (2007)
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| Department: | Department of Computer Engineering and Software Engineering |
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| ISBN: | 1424411645 |
| PolyPublie URL: | https://publications.polymtl.ca/21864/ |
| Conference Title: | IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007) |
| Conference Location: | Montréal, Québec |
| Conference Date(s): | 2007-08-05 - 2007-08-08 |
| Publisher: | Institute of Electrical and Electronics Engineers |
| DOI: | 10.1109/newcas.2007.4487953 |
| Official URL: | https://doi.org/10.1109/newcas.2007.4487953 |
| Date Deposited: | 18 Apr 2023 15:16 |
| Last Modified: | 08 Apr 2025 02:09 |
| Cite in APA 7: | Hireche, N., Langlois, J. M. P., & Nicolescu, G. (2007, August). A systolic array for sequence comparison based on two logic levels processing element [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. https://doi.org/10.1109/newcas.2007.4487953 |
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