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Ebrahimi, A., Pullu, V. N., Langlois, J. M. P., & David, J. P. Iterative pruning algorithm for efficient look-up table implementation of binary neural networks [Paper]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). External link
Traore, M., Langlois, J. M. P., & David, J. P. (2022, June). ASIP accelerator for LUT-based neural networks inference [Paper]. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada. External link
Luinaud, T., Langlois, J. M. P., & Savaria, Y. (2022). Symbolic analysis for data plane programs specialization. ACM Transactions on Architecture and Code Optimization, 20(1), 1-21. External link
Luinaud, T., Santiago da Silva, J., Langlois, J. M. P., & Savaria, Y. (2021, February). Design Principles for Packet Deparsers on FPGAs [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2021) (7 pages). Available
Ahmadi, M., Vakili, S., & Langlois, J. M. P. (2021). CARLA: A Convolution Accelerator with a Reconfigurable and Low-Energy Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(8), 3184-3196. External link
Lévesque, M., Gao, H.Y., Southward, C., Langlois, J. M. P., Léna, C., & Courtemanche, R. (2020). Cerebellar Cortex 4-12 Hz Oscillations and Unit Phase Relation in the Awake Rat. Frontiers in Systems Neuroscience, 14, 475948 (17 pages). Available
Luinaud, T., Stimpfling, T., Santiago da Silva, J., Savaria, Y., & Langlois, J. M. P. (2020, May). Bridging the gap: FPGAs as programmable switches [Paper]. 21st IEEE International Conference on High Performance Switching and Routing (HPSR 2020) (7 pages). External link
Ahmadi, M., Vakili, S., & Langlois, J. M. P. (2020, June). An energy-efficient accelerator architecture with serial accumulation dataflow for deep CNNs [Paper]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Québec. External link
Ahmadi, M., Vakili, S., & Langlois, J. M. P. (2020, June). Heterogeneous distributed SRAM configuration for energy-efficient deep CNN accelerators [Paper]. 18th IEEE International New Circuits and Systems Conference (NEWCAS 2020), Montréal, Québec. External link
Chidambaram, S., Langlois, J. M. P., & David, J. P. (2020, March). PoET-BiN : Power Efficient Tiny Binary Neurons [Paper]. 3rd Conference on Machine Learning and Systems (MLSys 2020), Austin, Texas (12 pages). Unavailable
Abdelsalam, A. M., Elsheikh, A., Chidambaram, S., David, J. P., & Langlois, J. M. P. (2020). POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. Journal of Signal Processing Systems, 92(1), 95-107. External link
Luinaud, T., Stimpfling, T., Santiago Da Silva, J., Savaria, Y., & Langlois, J. M. P. (2020, February). Unleashing the Power of FPGAs as Programmable Switches [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2020), Seaside, CA, USA (1 page). External link
Santiago Da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (2019, April). Module-per-object: A human-driven methodology for c++-based high-level synthesis design [Paper]. 27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2019), San Diego, CA, United states. External link
Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (2019, October). POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests [Paper]. 13th Conference on Design and Architectures for Signal and Image Processing (DASIP 2019), Montréal, Qc, Canada. External link
Stimpfling, T., Belanger, N., Langlois, J. M. P., & Savaria, Y. (2019). SHIP: a scalable high-performance IPv6 lookup algorithm that exploits prefix characteristics. IEEE/ACM Transactions on Networking, 27(4), 1529-1542. External link
Chidambaram, S., Riviello, A., Langlois, J. M. P., & David, J. P. (2018, October). Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors [Paper]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal. External link
Léonardon, M., Leroux, C., Binet, D., Langlois, J. M. P., Jégo, C., & Savaria, Y. (2018, May). Custom low power processor for polar decoding [Paper]. IEEE International Symposium on Circuits & Systems (ISCAS 2018), Florence, Italy. External link
Abdelsalam, A. M., Boulet, F., Demers, G., Langlois, J. M. P., & Cheriet, F. (2018, December). An Efficient FPGA-based Overlay Inference Architecture for Fully Connected DNNs [Paper]. International Conference on ReConFigurable Computing and FPGAs (ReConFig 2018), Cancun, Mexico (6 pages). External link
Vakili, S., Langlois, J. M. P., Savaria, Y., & Manjikian, N. (2018). Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Communications, 12(7), 868-875. External link
Mosleh, A., Elmi Sola, Y., Zargari, F., Onzon, E., & Langlois, J. M. P. (2018). Explicit ringing removal in image deblurring. IEEE Transactions on Image Processing, 27(2), 580-593. External link
Santiago da Silva, J., Boyer, F.-R., Chiquette, L.-O., & Langlois, J. M. P. (2018, June). Extern objects in P4: an ROHC compressing scheme case study [Paper]. IEEE Conference on Network Softwarization (NetSoft 2018), Montréal, Québec. External link
Bendaoudi, H., Cheriet, F., Manraj, A., Ben Tahar, H., & Langlois, J. M. P. (2018). Flexible architectures for retinal blood vessel segmentation in high-resolution fundus images. Journal of Real-Time Image Processing, 15(1), 31-42. External link
Stimpfling, T., Langlois, J. M. P., Bélanger, N., & Savaria, Y. (2018, May). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis [Paper]. 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.. External link
Santiago da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (2018, February). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA. External link
Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (2018, October). POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA [Paper]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal. External link
Ahmadi, M., Vakili, S., Langlois, J. M. P., & Gross, W. J. (2018, June). Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy [Paper]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. External link
Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017). Efficient realization of BCD multipliers using FPGAs. International Journal of Reconfigurable Computing, 2017, 1-12. Available
Lacroix, A. B., Langlois, J. M. P., Boyer, F.-R., Gosselin, A., & Bois, G. (2016, March). Node configuration for the Aho-Corasick algorithm in intrusion detection systems [Poster]. ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, Californie (2 pages). Available
Abdelsalam, A. M., Langlois, J. M. P., & Cheriet, F. (2017, February). Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only) [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, CA, USA. External link
Abdelsalam, A. M., Langlois, J. M. P., & Cheriet, F. (2017, April). A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation [Paper]. 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2017), Napa, California. External link
Gao, S., Al-Khalili, D., Langlois, J. M. P., & Chabini, N. (2017, April). Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier [Paper]. 30th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2017), Windsor, ON, Canada (6 pages). External link
Luinaud, T., Savaria, Y., & Langlois, J. M. P. (2017, May). An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search [Paper]. Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta. External link
Luinaud, T., Savaria, Y., & Langlois, J. M. P. (2017, February). An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only) [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, California. External link
Bendaoudi, H., Cheriet, F., & Langlois, J. M. P. (2016, October). Memory efficient multi-scale line detector architecture for retinal blood vessel segmentation [Paper]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2016), Rennes, France. External link
Sarbishei, I., Vakili, S., Langlois, J. M. P., & Savaria, Y. (2017, May). Scalable memory-less architecture for string matching with FPGAs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD. External link
Vakili, S., Langlois, J. M. P., & Bois, G. (2016). Accuracy-aware processor customisation for fixed-point arithmetic. IET Computers and Digital Techniques, 10(1), 1-11. External link
Farah, R., Langlois, J. M. P., & Bilodeau, G.-A. (2016). Computing a rodent's diary. Signal, Image and Video Processing, 10(3), 567-574. External link
Gan, Q., Séoud, L., Ben Tahar, H., & Langlois, J. M. P. (2016, April). Memory efficient and constant time 2D-recursive spatial averaging filter for embedded implementations [Paper]. Real-Time Image and Video Processing 2016, part of Photonics Europe 2016, Brussels, Belgium. External link
Vakili, S., Langlois, J. M. P., Boughzala, B., & Savaria, Y. (2016, March). Memory-efficient string matching for intrusion detection systems using a high-precision pattern grouping algorithm [Paper]. 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California. External link
Séoud, L., Hurtut, T., Chelbi, J., Cheriet, F., & Langlois, J. M. P. (2016). Red lesion detection using dynamic shape features for diabetic retinopathy screening. IEEE Transactions on Medical Imaging, 35(4), 1116-1126. External link
Bilodeau, G.-A., Desgent, S., Farah, R., Duss, S., Langlois, J. M. P., & Carmant, L. (2015). Body temperature measurement of an animal by tracking in biomedical experiments. Signal Image and Video Processing, 9(2), 251-259. External link
Mosleh, A., Green, P., Onzon, E., Begin, I., & Langlois, J. M. P. (2015, June). Camera intrinsic blur kernel estimation: A reliable framework [Paper]. IEEE Conference on Computer Vision and Pattern Recognition (CVPR 2015), Boston, MA, United states. External link
Vakili, S., Langlois, J. M. P., & Bois, G. (2015, June). Designing Customized Microprocessors for Fixed-Point Computation [Paper]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec. External link
Bendaoudi, H., Gan, Q., Cheriet, F., Ben Tahar, H., & Langlois, J. M. P. (2015, December). A run-length encoding co-processor for retinal image texture analysis [Paper]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Mexico City, Mexico (6 pages). External link
Séoud, L., Faucon, T., Hurtut, T., Chelbi, J., Cheriet, F., & Langlois, J. M. P. (2014, April). Automatic detection of microaneurysms and haemorrhages in fundus images using dynamic shape features [Paper]. 11th IEEE International Symposium on Biomedical Imaging (ISBI 2014), Beijing, China. External link
Farah, R., Gan, Q., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (2014). A computationally efficient importance sampling tracking algorithm. Machine Vision and Applications, 25(7), 1761-1777. External link
Gan, Q. F., Langlois, J. M. P., & Savaria, Y. (2014). Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations. Journal of Signal Processing Systems for Signal Image and Video Technology, 75(3), 191-202. External link
Mosleh, A., Langlois, J. M. P., & Green, P. (2014, September). Image deconvolution ringing artifact detection and removal via psf frequency analysis [Paper]. 13th European Conference on Computer Vision (ECCV 2014), Zurich, Switzerland. External link
Keklikian, T., Langlois, J. M. P., & Savaria, Y. (2014, June). A Memory Transaction Model for Sparse Matrix-Vector Multiplications on GPUs [Paper]. 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivières, Canada. External link
Gan, Q., Langlois, J. M. P., & Savaria, Y. (2014). A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems. Circuits, Systems & Signal Processing, 33(11), 3591-3602. External link
Fasih, M., Langlois, J. M. P., & Cheriet, F. (2014, February). Retinal image quality assessment using generic features [Paper]. SPIE Medical Imaging, San Diego, California, USA. External link
Bendaoudi, H., Cheriet, F., Ben Tahar, H., & Langlois, J. M. P. (2014, October). A Scalable Hardware Architecture for Retinal Blood Vessel Detection in High Resolution Fundus Images [Paper]. Conference on Design & Architectures for Signal & Image Processing (DASIP 2014), Madrid, Spain. External link
Gill, D. C., Langlois, J. M. P., & Savaria, Y. (2013, October). Accelerating a modified gaussian pyramid with a customized processor [Paper]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2013), Cagliari, Italy. External link
Farah, R., Langlois, J. M. P., & Bilodeau, G.-A. (2013). Catching a rat by its edglets. IEEE Transactions on Image Processing, 22(2), 668-678. External link
Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Customised soft processor design: A compromise between architecture description languages and parameterisable processors. IET Computers and Digital Techniques, 7(3), 122-131. External link
Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(12), 1853-1865. External link
Vakili, S., Langlois, J. M. P., & Bois, G. (2013, May). Finite-precision error modeling using affine arithmetic [Paper]. 38th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013), Vancouver, BC, Canada. External link
Gan, Q., Langlois, J. M. P., & Savaria, Y. (2013). Parallel array histogram architecture for embedded implementations. Electronics Letters, 49(2), 99-101. External link
Gan, Q., Langlois, J. M. P., & Savaria, Y. (2013, August). A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor [Paper]. 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2013), Columbus, OH, USA. External link
Gao, S., Al-Khalili, D., Chabini, N., & Langlois, J. M. P. (2012). Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Computers and Digital Techniques, 6(6), 372-83. External link
Bilodeau, G.-A., Torabi, A., Levesque, M., Ouellet, C., Langlois, J. M. P., Lema, P., & Carmant, L. (2012). Body Temperature Estimation of a Moving Subject From Thermographic Images. Machine Vision and Applications, 23(2), 299-311. External link
Mahvash Mohammadi, H., Savaria, Y., & Langlois, J. M. P. (2012). Enhanced motion compensated deinterlacing algorithm. IET Image Processing, 6(8), 1041-1048. External link
Aubertin, P., Langlois, J. M. P., & Savaria, Y. (2012). Real-time computation of local neighborhood functions in application-specific instruction-set processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(11), 2031-2043. External link
Athow, J. L., Rozon, C., Al-Khalili, D., & Langlois, J. M. P. (2011, December). A CNFET-based characterization framework for digital circuits [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link
Rajotte, S., Carolina Gil, D., & Langlois, J. M. P. (2011, May). Combining ISA extensions and subsetting for improved ASIP performance and cost [Paper]. IEEE International Symposium of Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil. External link
Gil, D. C., Farah, R., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (2011, May). Comparative analysis of contrast enhancement algorithms in surveillance imaging [Paper]. IEEE International Symposium of Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil. External link
Vakili, S., Gil, D. C., Langlois, J. M. P., Savaria, Y., & Bois, G. (2011, December). Customized embedded processor design for global photographic tone mapping [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link
Mohammadi, H. M., Savaria, Y., & Langlois, J. M. P. (2011). Hybrid video deinterlacing algorithm exploiting reverse motion estimation. IET Image Processing, 5(7), 611-618. External link
Farah, R., Langlois, J. M. P., & Bilodeau, G.-A. (2011, September). RAT: Robust animal tracking [Paper]. 9th IEEE International Symposium on Robotic and Sensors Environments (ROSE 2011), Montréal, Québec. External link
Farah, R., Gan, Q., Langlois, J. M. P., Bilodeau, G.-A., & Savaria, Y. (2011, December). A tracking algorithm suitable for embedded systems implementation [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link
Bilodeau, G.-A., Ghali, R., Desgent, S., Langlois, J. M. P., Farah, R., St-Onge, P.-L., Duss, S., & Carmant, L. (2011, June). Where is the rat? Tracking in low contrast thermographic images [Paper]. IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops (CVPRW 2011), Colorado Springs, CO, United states. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2010). FPGA-based efficient design approaches for large size two's complement squarers. Journal of Signal Processing Systems, 58(1), 3-15. External link
Islam, A., Iqbal, U., Langlois, J. M. P., & Noureldin, A. (2010). Implementation methodology of embedded land vehicle positioning using an integrated GPS and multi sensor system. Integrated Computer-Aided Engineering, 17(1), 69-83. External link
Allaire, F. C. J., Langlois, J. M. P., Labonté, G., & Tarbouchi, M. (2010, October). Two-tiered resolution real-time path evaluation [Paper]. International Conference on Evolutionary Computation, Valencia, Spain. External link
Islam, A., Langlois, J. M. P., & Noureldin, A. (2009, June). A design methodology for the implementation of embedded vehicle navigation systems [Paper]. IEEE International Conference on Electro/Information Technology, Windsor, ON, Canada. External link
Aubertin, P., Mohammadi, H. M., Savaria, Y., & Langlois, J. M. P. (2009, June). High performance ASIP implementation of PBDI: a new intra-field deinterlacing method [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link
Levesque, M., Langlois, J. M. P., Lema, P., Courtemanche, R., Bilodeau, G.-A., & Carmant, L. (2009). Synchronized Gamma Oscillations (30-50 Hz) in the Amygdalo-Hippocampal Network in Relation With Seizure Propagation and Severity. Neurobiology of Disease, 35(2), 209-218. External link
Bilodeau, G.-A., Levesque, M., Langlois, J. M. P., Lema, P., & Carmant, L. (2009, January). Thermographic body temperature measurement using a mean-shift tracker [Paper]. 2nd International Conference on Bio-Inspired Systems and Signal Processing (BIOSIGNALS 2009), Porto, Portugal. External link
Fontaine, S., Goyette, S., Langlois, J. M. P., & Bois, G. (2008, October). Acceleration of a 3D target tracking algorithm using an application specific instruction set processor [Paper]. IEEE International Conference on Computer Design (ICCD 2008). External link
Daigneault, M.-A., Langlois, J. M. P., & David, J. P. (2008, October). Application Specific Instruction set processor specialized for block motion estimation [Paper]. IEEE International Conference on Computer Design (ICCD 2008), Lake Tahoe, CA. External link
Kong, M. Y., Langlois, J. M. P., & Al-Khalili, D. (2008, May). Efficient FPGA implementation of complex multipliers using the logarithmic number system [Paper]. IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, United states. External link
Bouyela Ngoyi, G.-A., Langlois, J. M. P., & Savaria, Y. (2008, June). Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link
Lévesque, M., Lema, P., Langlois, J. M. P., Courtemanche, R., & Carmant, L. (2008). Local field potential synchrony in the amygdalo-hippocampal network during kainate induced-seizures. External link
Torabi, A., Bilodeau, G.-A., Levesque, M., Langlois, J. M. P., Lema, P., & Carmant, L. (2008, December). Measuring an animal body temperature in thermographic video using particle filter tracking [Paper]. 4th International Symposium on Visual Computing (ISVC 2008), Las Vegas, Nevada. External link
Tchoulack, S., Langlois, J. M. P., & Cheriet, F. (2008, June). A video stream processor for real-time detection and correction of specular reflections in endoscopic images [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. External link
Mohammadi, H. M., Langlois, J. M. P., & Savaria, Y. (2007). A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Transactions on Consumer Electronics, 53(3), 1117-1124. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007, July). FPGA-based efficient design approach for large-size two's complement squarers [Paper]. IEEE International Conference on Application-specific Systems, Architectures and Processors, Montréal, Québec. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2007). Optimised Realisations of Large Integer Multipliers and Squarers Using Embedded Blocks. IET Computers and Digital Techniques, 1(1), 9-16. External link
Hireche, N., Langlois, J. M. P., & Nicolescu, G. (2007, August). A systolic array for sequence comparison based on two logic levels processing element [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. External link
Langlois, J. M. P., & Al-Khalili, D. (2006). Carry-free approximate squaring functions with O(n) complexity and O(1) delay. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(5), 374-378. External link
Langlois, J. M. P. (2006, June). Design and implementation of high sampling rate programmable FIR filters in FPGAs [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, September). Efficient FPGA-based realization of complex squarer and complex conjugate using embedded mulitpliers [Paper]. IEEE International SOC Conference (SOCC 2006). External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, June). Efficient realization of large integers multipliers and squarers [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2006, March). An optimized design approach for squaring large integers using embedded hardwired multipliers [Paper]. ACS/IEEE International Conference on Computer Systems and Applications. External link
Mahvash, M. H., Savaria, Y., & Langlois, J. M. P. (2006, June). Real-time ELA de-interlacing with the Xtensa reconfigurable processor [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Hireche, N., Langlois, J. M. P., & Nicolescu, G. (2006, May). Survey of biological high performance computing: Algorithms, implementations and outlook research [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2006), Ottawa, Ontario. External link
Mohammadi, H. M., Langlois, J. M. P., & Savaria, Y. (2006, December). A threshold-based deinterlacing algorithm using motion compensation and directional interpolation [Paper]. 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France. External link
Gilbert, G., & Langlois, J. M. P. (2005, June). Multipath greedy algorithm for canonical representation of numbers in the double base number system [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, Canada. External link
Gao, S., Chabini, N., Al-Khalili, D., & Langlois, J. M. P. (2005, November). Optimized multipliers for large unsigned integers [Paper]. NORCHIP Conference, Oulu, Finlande. External link
Langlois, J. M. P., Al-Khalili, D., & Al-Hertani, H. '. (2004, June). Carry free, bit parallel approximate squarers with linear complexity and constant delay [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link
Langlois, J. M. P. (2004, May). Design of linear phase FIR filters using particle swarm optimization [Paper]. 22nd Biennial Symposium on Communications, Kingston, Canada. Unavailable
Langlois, J. M. P., & Al-Khalili, D. (2004). Phase to sinusoid amplitude conversion techniques for direct digital frequency synthesis. IEE Proceedings-Circuits, Devices and Systems, 151(6), 519-528. External link
Langlois, J. M. P., & Al-Khalili, D. (2003, September). Low power direct digital frequency synthesizers in 0.18 μm CMOS [Paper]. IEEE Custom Integrated Circuits Conference (CICC 2003), San José, CA, USA. External link
Langlois, J. M. P., & Al-Khalili, D. (2003). Novel approach to the design of direct digital frequency synthesizers based on linear interpolation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 50(9), 567-578. External link
Langlois, J. M. P. (2003). Novel design approach and architectures for sinusoid output direct digital frequency synthesis [Ph.D. Thesis, Royal Military College of Canada]. External link
Al-Khalili, D., & Langlois, J. M. P. (2003). Phase to sine amplitude conversion system and method. (Patent no. US6657573). External link
Langlois, J. M. P., & Al-Khalili, D. (2003, June). Piecewise continuous linear interpolation of the sine function for direct digital frequency synthesis [Paper]. IEEE MTT-S International Microwave Symposium (IMS 2003), Philadelphia, PA, USA. External link
Liu, Q., Langlois, J. M. P., Al-Khalili, D., Szwarc, V., & Ink, R. (2003, May). Synthesis of a 12-bit complex mixer for FPGA implementation [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), Montréal, Québec. External link
Langlois, J. M. P., & Al-Khalili, D. (2002, May). Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2002), Scottsdale, Arizona, USA. External link
Langlois, J. M. P., & Al-Khalili, D. (2002, April). A low power direct digital frequency synthesizer with 60 dBc spectral purity [Paper]. 12th ACM Great Lakes symposium on VLSI, New York, NY, USA. External link
Langlois, J. M. P., & Al-Khalili, D. (2002, May). A new approach to the design of low power direct digital frequency synthesizers [Paper]. IEEE International Frequency Control Symposium and PDA Exhibition, New Orleans, USA. External link
Langlois, J. M. P., Al-Khalili, D., & Inkol, R. J. (2002). Polyphase filter approach for high performance, FPGA-based quadrature demodulation. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 32(3), 237-254. External link
Langlois, J. M. P., & Al-Khalili, D. (2001, August). ROM size reduction with low processing cost for direct digital frequency synthesis [Paper]. IEEE Pacific Rim Conference on Communications, Computers and signal Processing (PACRIM 2001), Victoria, Canada. External link
Langlois, J. M. P. (2000). Design and implementation of wide band quadrature demodulators on field programmable gate arrays [Master's Thesis, Royal Military College of Canada]. External link
Langlois, J. M. P., Al-Khalili, D., & Inkol, R. J. (1999, May). A high performance, wide bandwidth, low cost FPGA-based quadrature demodulator [Paper]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 1999), Edmonton, Canada. External link
