Q. Gan, J. M. Pierre Langlois
and Yvon Savaria
Article (2013)
An external link is available for this item
| Department: |
Department of Computer Engineering and Software Engineering Department of Electrical Engineering |
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| Research Center: | GR2M - Microelectronics and Microsystems Research Group |
| PolyPublie URL: | https://publications.polymtl.ca/13881/ |
| Journal Title: | Electronics Letters (vol. 49, no. 2) |
| Publisher: | IET |
| DOI: | 10.1049/el.2012.2701 |
| Official URL: | https://doi.org/10.1049/el.2012.2701 |
| Date Deposited: | 18 Apr 2023 15:09 |
| Last Modified: | 25 Sep 2024 15:51 |
| Cite in APA 7: | Gan, Q., Langlois, J. M. P., & Savaria, Y. (2013). Parallel array histogram architecture for embedded implementations. Electronics Letters, 49(2), 99-101. https://doi.org/10.1049/el.2012.2701 |
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