M. S. Njinowa, H. T. Bui and François-Raymond Boyer
Paper (2010)
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| Department: | Department of Computer Engineering and Software Engineering |
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| Research Center: | GR2M - Microelectronics and Microsystems Research Group |
| PolyPublie URL: | https://publications.polymtl.ca/17818/ |
| Conference Title: | IEEE International Symposium on Circuits and Systems. ISCAS 2010 |
| Conference Location: | Paris, France |
| Conference Date(s): | 2010-05-30 - 2010-06-02 |
| Publisher: | Institute of Electrical and Electronics Engineers |
| DOI: | 10.1109/iscas.2010.5537254 |
| Official URL: | https://doi.org/10.1109/iscas.2010.5537254 |
| Date Deposited: | 18 Apr 2023 15:13 |
| Last Modified: | 25 Sep 2024 15:55 |
| Cite in APA 7: | Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (2010, May). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS) [Paper]. IEEE International Symposium on Circuits and Systems. ISCAS 2010, Paris, France. https://doi.org/10.1109/iscas.2010.5537254 |
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