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Bui, H. T., & Savaria, Y. (2006, April). High speed differential pulse-width control loop based on frequency-to-voltage converters [Paper]. 16th ACM Great Lakes Symposium on VLSI (GLSVLSI 2006), Philadelphia, USA. External link
Bui, H. T. (2006). High-speed CMOS design techniques for multi-gigahertz transceivers [Ph.D. thesis, École Polytechnique de Montréal]. Available
Bui, H. T., & Savaria, Y. (2005, July). A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in Socs [Paper]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada. External link
Bui, H. T., & Savaria, Y. (2005, June). High-speed differential frequency-to-voltage converter [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005). External link
Bui, H. T., & Savaria, Y. (2004, July). 10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 mu m CMOS [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link
Bui, H. T., & Savaria, Y. (2004, May). Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada. External link
Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (2013, June). Design of low power 4-bit flash ADC based on standard cells [Paper]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France (4 pages). External link
Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (2010, May). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS) [Paper]. IEEE International Symposium on Circuits and Systems. ISCAS 2010, Paris, France. External link
Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (2009, June). Design and optimization of a low complexity all-digital digital-to-analog converter [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (2008, June). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (2007, May). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana. External link
Pontikakis, B., Boyer, F.-R., Savaria, Y., & Bui, H. T. (2007, August). Precise free-running period synthesizer (FRPS) with process and temperature compensation [Paper]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007). External link
Vezant, B., Mansuy, C., Bui, H. T., & Boyer, F.-R. (2009, June). Direct digital synthesis-based all-digital phase-locked loop [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link
