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Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (juin 2013). Design of low power 4-bit flash ADC based on standard cells [Communication écrite]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France (4 pages). Lien externe
Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (mai 2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana. Lien externe
Bui, H. T. (2006). High-speed CMOS design techniques for multi-gigahertz transceivers [Thèse de doctorat, École Polytechnique de Montréal]. Disponible