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A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs

B. Pontikakis, H. T. Bui, François-Raymond Boyer and Yvon Savaria

Paper (2008)

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Department: Department of Computer Engineering and Software Engineering
Department of Electrical Engineering
PolyPublie URL: https://publications.polymtl.ca/20334/
Conference Title: Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008)
Conference Date(s): 2008-06-22 - 2008-06-25
Publisher: IEEE
DOI: 10.1109/newcas.2008.4606396
Official URL: https://doi.org/10.1109/newcas.2008.4606396
Date Deposited: 18 Apr 2023 15:16
Last Modified: 05 Apr 2024 11:03
Cite in APA 7: Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (2008, June). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). https://doi.org/10.1109/newcas.2008.4606396

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