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A high-speed, scalable, and programmable traffic manager architecture for flow-based networking

Imad Benacer, François-Raymond Boyer and Yvon Savaria

Article (2019)

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Cite this document: Benacer, I., Boyer, F.-R. & Savaria, Y. (2019). A high-speed, scalable, and programmable traffic manager architecture for flow-based networking. IEEE Access, 7, p. 2231-2243. doi:10.1109/access.2018.2886230
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In this paper, we present a programmable and scalable traffic manager (TM) architecture, targeting requirements of high-speed networking devices, especially in the software-defined networking context. This TM is intended to ease the deployability of new architectures through field-programmable gate array (FPGA) platforms and to make the data plane programmable and scalable. Flow-based networking allows treating traffic in terms of flows rather than as a simple aggregation of individual packets, which simplifies scheduling and bandwidth allocation for each flow. Programmability brings agility, flexibility, and rapid adaptation to changes, allowing to meet network requirements in real-time. Traffic management with fast queuing and reduced latency plays an important role to support the upcoming 5G cellular communication technology. The proposed TM architecture is coded in C++ and is synthesized with the Vivado High-Level Synthesis tool. This TM is capable of supporting links operating beyond 40 Gb/s, on the ZC706 board and XCVU440-FLGB2377-3-E FPGA device from Xilinx, while achieving 80 Gb/s and 100 Gb/s throughput, respectively. The resulting placed and routed design was tested on the ZC706 board with its embedded ARM processor controlling table updates.

Uncontrolled Keywords

traffic manager (TM); flow-based networking; data plane; high-level synthesis (HLS); field-programmable gate array (FPGA); 5G

Open Access document in PolyPublie
Subjects: 2500 Génie électrique et électronique > 2500 Génie électrique et électronique
2700 Technologie de l'information > 2700 Technologie de l'information
Department: Département de génie électrique
Département de génie informatique et génie logiciel
Research Center: GR2M - Groupe de recherche en microélectronique et microsystèmes
ResMIQ - Regroupement stratégique en microsystèmes du Québec
Funders: CRSNG/NSERC, Prompt Québec, Ericsson Research Canada, Mitacs, Kaloom
Date Deposited: 08 Apr 2021 10:23
Last Modified: 09 Apr 2021 01:20
PolyPublie URL: https://publications.polymtl.ca/4781/
Document issued by the official publisher
Journal Title: IEEE Access (vol. 7)
Publisher: IEEE
Official URL: https://doi.org/10.1109/access.2018.2886230


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