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Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). HPQS: A fast, high-capacity, hybrid priority queuing system for high-speed networking devices. IEEE Access, 7, 130672-130684. Available
Benacer, I. (2019). Fast, Scalable, and Flexible C++ Hardware Architectures for Network Data Plane Queuing and Traffic Management [Ph.D. thesis, Polytechnique Montréal]. Available
Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). A high-speed, scalable, and programmable traffic manager architecture for flow-based networking. IEEE Access, 7, 2231-2243. Available
Benacer, I., Boyer, F.-R., & Savaria, Y. (2018, May). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). External link
Benacer, I., Boyer, F.-R., & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952. External link
Benacer, I., Boyer, F.-R., & Savaria, Y. (2018, June). HPQ: a high capacity hybrid priority queue architecture for high-speed network switches [Paper]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec. External link
Benacer, I., Boyer, F.-R., & Savaria, Y. (2017, June). A high-speed traffic manager architecture for flow-based networking [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link
Benacer, I., Boyer, F.-R., Bélanger, N., & Savaria, Y. (2016, June). A fast systolic priority queue architecture for a flow-based Traffic Manager [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). External link
