Fast, Scalable, and Flexible C++ Hardware Architectures for Network Data Plane Queuing and Traffic Management

Imad Benacer

Ph.D. thesis (2019)

Open Access document in PolyPublie

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Department:	Department of Computer Engineering and Software Engineering
Program:	Génie informatique
Academic/Research Directors:	François-Raymond Boyer and Yvon Savaria
PolyPublie URL:	https://publications.polymtl.ca/3812/
Institution:	Polytechnique Montréal
Date Deposited:	12 Jun 2019 10:59
Last Modified:	01 Apr 2026 20:27

Cite in APA 7:	Benacer, I. (2019). Fast, Scalable, and Flexible C++ Hardware Architectures for Network Data Plane Queuing and Traffic Management [Ph.D. thesis, Polytechnique Montréal]. PolyPublie. https://publications.polymtl.ca/3812/
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