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Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis

Imad Benacer, François-Raymond Boyer and Yvon Savaria

Paper (2018)

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Department: Department of Computer Engineering and Software Engineering
Department of Electrical Engineering
Research Center: GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL: https://publications.polymtl.ca/39566/
Conference Title: IEEE International Symposium on Circuits and Systems (ISCAS 2018)
Conference Location: Florence, Italy
Conference Date(s): 2018-05-27 - 2018-05-30
Publisher: IEEE
DOI: 10.1109/iscas.2018.8351332
Official URL: https://doi.org/10.1109/iscas.2018.8351332
Date Deposited: 18 Apr 2023 15:02
Last Modified: 05 Apr 2024 11:35
Cite in APA 7: Benacer, I., Boyer, F.-R., & Savaria, Y. (2018, May). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). https://doi.org/10.1109/iscas.2018.8351332

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