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A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue

Imad Benacer, François-Raymond Boyer and Yvon Savaria

Article (2018)

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Department: Department of Computer Engineering and Software Engineering
Department of Electrical Engineering
Research Center: GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL: https://publications.polymtl.ca/41474/
Journal Title: IEEE Transactions on Very Large Scale Integration (VLSI) Systems (vol. 26, no. 10)
Publisher: IEEE
DOI: 10.1109/tvlsi.2018.2838044
Official URL: https://doi.org/10.1109/tvlsi.2018.2838044
Date Deposited: 18 Apr 2023 15:02
Last Modified: 05 May 2023 15:46
Cite in APA 7: Benacer, I., Boyer, F.-R., & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952. https://doi.org/10.1109/tvlsi.2018.2838044

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