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A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications

François-Raymond Boyer, H. G. Epassa, B. Pontikakis, Yvon Savaria and W. Ling

Paper (2004)

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Additional Information: Nom historique du département: Département de génie informatique
Department: Department of Electrical Engineering
Department of Computer Engineering and Software Engineering
PolyPublie URL: https://publications.polymtl.ca/25237/
Conference Title: 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004)
Conference Location: Montréal, Québec
Conference Date(s): 2004-06-20 - 2004-06-23
Publisher: IEEE
DOI: 10.1109/newcas.2004.1359043
Official URL: https://doi.org/10.1109/newcas.2004.1359043
Date Deposited: 18 Apr 2023 15:19
Last Modified: 05 Apr 2024 11:11
Cite in APA 7: Boyer, F.-R., Epassa, H. G., Pontikakis, B., Savaria, Y., & Ling, W. (2004, June). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. https://doi.org/10.1109/newcas.2004.1359043

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