Y. Blaquiere, Michel Dagenais
and Yvon Savaria
Article (1996)
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| Additional Information: | Nom historique du département: Département de génie électrique et de génie informatique |
|---|---|
| Department: |
Department of Electrical Engineering Department of Computer Engineering and Software Engineering |
| PolyPublie URL: | https://publications.polymtl.ca/31492/ |
| Journal Title: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (vol. 15, no. 2) |
| Publisher: | IEEE |
| DOI: | 10.1109/43.486669 |
| Official URL: | https://doi.org/10.1109/43.486669 |
| Date Deposited: | 18 Apr 2023 15:24 |
| Last Modified: | 25 Sep 2024 16:13 |
| Cite in APA 7: | Blaquiere, Y., Dagenais, M., & Savaria, Y. (1996). Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), 244-255. https://doi.org/10.1109/43.486669 |
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