Dorin Emil Calbaza and Yvon Savaria
Paper (1999)
An external link is available for this itemAdditional Information: | Nom historique du département: Département de génie électrique et de génie informatique |
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Department: |
Department of Electrical Engineering Department of Computer Engineering and Software Engineering |
PolyPublie URL: | https://publications.polymtl.ca/29070/ |
Conference Title: | IEEE International Symposium on Circuits and Systems (ISCAS 1999) |
Conference Location: | Orlando, FL, USA |
Conference Date(s): | 1999-05-30 - 1999-06-02 |
Publisher: | IEEE |
DOI: | 10.1109/iscas.1999.777791 |
Official URL: | https://doi.org/10.1109/iscas.1999.777791 |
Date Deposited: | 18 Apr 2023 15:22 |
Last Modified: | 25 Sep 2024 16:10 |
Cite in APA 7: | Calbaza, D. E., & Savaria, Y. (1999, May). Jitter model of direct digital synthesis clock generators [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. https://doi.org/10.1109/iscas.1999.777791 |
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