Omar Al-Terkawi Hasib, Daniel Crepeau, Thomas Awad, Andrei Dulipovici, Yvon Savaria
and Claude Thibeault
Paper (2018)
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| Department: | Department of Electrical Engineering |
|---|---|
| Research Center: | GR2M - Microelectronics and Microsystems Research Group |
| ISBN: | 9781538637746 |
| PolyPublie URL: | https://publications.polymtl.ca/40397/ |
| Conference Title: | 36th IEEE VLSI Test Symposium (VTS 2018) |
| Conference Location: | Los Alamitos, CA |
| Conference Date(s): | 2018-04-22 - 2018-04-25 |
| Publisher: | IEEE |
| DOI: | 10.1109/vts.2018.8368637 |
| Official URL: | https://doi.org/10.1109/vts.2018.8368637 |
| Date Deposited: | 18 Apr 2023 15:03 |
| Last Modified: | 08 Apr 2025 12:22 |
| Cite in APA 7: | Hasib, O. A.-T., Crepeau, D., Awad, T., Dulipovici, A., Savaria, Y., & Thibeault, C. (2018, April). Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits [Paper]. 36th IEEE VLSI Test Symposium (VTS 2018), Los Alamitos, CA (6 pages). https://doi.org/10.1109/vts.2018.8368637 |
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