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Hasib, O. A.-T., Crepeau, D., Awad, T., Dulipovici, A., Savaria, Y., & Thibeault, C. (2018, April). Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits [Paper]. 36th IEEE VLSI Test Symposium (VTS 2018), Los Alamitos, CA (6 pages). External link