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Benyoussef, M., Thibeault, C., & Savaria, Y. (mai 2019). A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). Lien externe
Bouanen, S., Thibeault, C., Savaria, Y., Tremblay, J.-P., & Zhu, G. (octobre 2013). Fault tolerant smart transducer interface for safety-critical avionics applications [Communication écrite]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. Lien externe
Chureau, A., Savaria, Y., Boland, J.-F., Zilic, Z., Thibeault, C., & Gagnon, F. (juin 2006). Building heterogeneous functional prototypes using articulated interfaces [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Darvishi, M., Audet, Y., Blaquiere, Y., Thibeault, C., & Pichette, S. (2019). On the susceptibility of SRAM-Based FPGA routing network to delay changes induced by ionizing radiation. IEEE Transactions on Nuclear Science, 66(3), 643-654. Lien externe
Darvishi, M., Audet, Y., Blaquiere, Y., Thibeault, C., Pichette, S., & Tazi, F. Z. (2014). Circuit level modeling of extra combinational delays in SRAM-based FPGAs due to transient ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3535-3542. Lien externe
El Mustapha Ait Yakoub, M., Sawan, M., & Thibeault, C. (juin 2009). A neuromimetic ultra low-power ADC for bio-sensing applications [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Lien externe
Fiorentino, M., Thibeault, C., & Savaria, Y. (2021). Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow. IET Computers & Digital Techniques, 15(6), 409-426. Disponible
Fiorentino, M., Thibeault, C., Savaria, Y., Gagnon, F., Awad, T., Morrissey, D., & Laurence, M. (mai 2019). AnARM: a 28nm energy efficient ARM processor based on Octasic asynchronous technology [Communication écrite]. 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan. Lien externe
Fiorentino, M., Savaria, Y., & Thibeault, C. (juin 2017). FPGA implementation of Token-based Self-timed processors: A case study [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. Lien externe
Fiorentino, M., Savaria, Y., Thibeault, C., & Gervais, P. (mai 2016). A practical design method for prototyping self-timed processors using FPGAs [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. Lien externe
Fiorentino, M., Al-Terkawi, O., Savaria, Y., & Thibeault, C. (juin 2015). Self-timed circuits FPGA implementation flow [Communication écrite]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Lien externe
Gagnon, F., Savaria, Y., Dumais, P., Ammari, M. L., & Thibeault, C. (2010). Multiequalizer unit used for telecommunications has decision unit, which receives corresponding synchronized signals and choose one synchronized signal that matches with predetermined transmission performance criterion signal. (Brevet no US7693490). Lien externe
Gagnon, Y., Savaria, Y., Meunier, M., & Thibeault, C. (octobre 1997). Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model [Communication écrite]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1997), Paris, Fr. Lien externe
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2020). Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. Journal of Electronic Testing-Theory and Applications, 35(6), 823-838. Lien externe
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2020). Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(3), 764-776. Lien externe
Hasib, O. A.-T., Crepeau, D., Awad, T., Dulipovici, A., Savaria, Y., & Thibeault, C. (avril 2018). Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits [Communication écrite]. 36th IEEE VLSI Test Symposium (VTS 2018), Los Alamitos, CA (6 pages). Lien externe
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (avril 2016). WeSPer: a flexible small delay defect quality metric [Communication écrite]. 34th IEEE VLSI Test Symposium (VTS 2016), Las Vegas, Nevada (6 pages). Lien externe
Hoque, K. A., Mohamed, O. A., Savaria, Y., & Thibeault, C. (octobre 2014). Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications [Communication écrite]. 12th ACM/IEEE International Conference on Methods and Models for System Design (MEMOCODE 2014), Lausanne, Switzerland. Lien externe
Hoque, K. A., Ait Mohamed, O., Savaria, Y., & Thibeault, C. (octobre 2013). Early analysis of soft error effects for aerospace applications using probabilistic model checking [Communication écrite]. 2nd International Workshop of Formal Techniques for Safety-Critical Systems (FTSCS 2013), Queenstown, New Zealand. Lien externe
Hobeika, C., Pichette, S., Ghodbane, A., Thibeault, C., Audet, Y., Boland, J.-F., & Saad, M. (2013). Flight control fault models based on SEU emulation. SAE International Journal of Aerospace, 6(2), 643-649. Lien externe
Joliveau, M., Giard, P., Gendreau, M., Gagnon, F., & Thibeault, C. (juin 2011). Design of low complexity multiplierless digital filters with optimized free structure using a population-based metaheuristic [Communication écrite]. International Symposium on Signals, Circuits and Systems, ISSCS 2011, Iasi, Romania. Lien externe
Joliveau, M., Gendreau, M., Gagnon, F., & Thibeault, C. (août 2011). Low complexity low power non-recursive digital filters with unconstrained topology [Communication écrite]. 20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden. Lien externe
Leduc-Primeau, F., Raymond, A. J., Giard, P., Cushon, K., Thibeault, C., & Gross, W. J. (octobre 2012). High-throughput LDPC decoding using the RHS algorithm [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany (6 pages). Lien externe
Monté-Genest, G., Antaki, B., Patenaude, S., Savaria, Y., Thibeault, C., & Trouborst, P. (avril 2001). Tools for the characterization of bipolar CML testability [Communication écrite]. 19th IEEE VLSI Test Symposium (VTS 2001), Marina Del Rey, CA, USA. Lien externe
Prieur, D., Granger, E., Savaria, Y., & Thibeault, C. (2016). Efficient identification of faces in video streams using low-power multi-core devices. Dans Handbook of pattern recognition and computer vision (5e éd.). Lien externe
Sahraii, N., Savaria, Y., Thibeault, C., & Gagnon, F. (juin 2008). Scheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). Lien externe
Tazi, F. Z., Thibeault, C., & Savaria, Y. (mai 2016). Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA [Communication écrite]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2016), Vancouver, British Columbia (5 pages). Lien externe
Tazi, F. Z., Thibeault, C., Savaria, Y., Pichette, S., & Audet, Y. (2014). On extra delays affecting I/O blocks of an SRAM-based FPGA due to ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3138-3145. Lien externe
Tremblay, J.-P., Savaria, Y., Zhu, G., Thibeault, C., & Bouanen, S. (octobre 2013). A hardware prototype for integration, test and validation of avionic networks [Communication écrite]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. Lien externe
Thibeault, C., Hariri, Y., Hasan, S. R., Hobeika, C., Savaria, Y., Audet, Y., & Tazi, F. Z. (2013). A library-based early soft error sensitivity analysis technique for SRAM-based FPGA design. Journal of Electronic Testing: Theory and Applications, 29(4), 457-471. Lien externe
Trentin, D., Savaria, Y., Zhu, G., & Thibeault, C. (octobre 2012). An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization [Communication écrite]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ. Publié dans SAE International Journal of Aerospace, 5(1). Lien externe
Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquière, Y., Moupfouma, F., & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65. Lien externe
Tremblay, J.-P., Savaria, Y., Zhu, G., Thibeault, C., & Bouanen, S. (octobre 2012). A System Architecture for Smart Sensors Integration in Avionics Applications [Communication écrite]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ. Publié dans SAE International Journal of Aerospace, 5(1). Lien externe
Tremblay, J.-P., Savaria, Y., Thibeault, C., & Mbaye, M. (octobre 2008). Improving resource utilization in an multiple asynchronous ALU DSP architecture [Communication écrite]. 1st Microsystems and Nanoelectronics Research Conference. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1994). A fast method to evaluate the optimum number of spares in defect-tolerant integrated-circuits. IEEE Transactions on Computers, 43(6), 687-697. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1992). Test quality of hierarchical defect-tolerant integrated circuits. Journal of Electronic Testing, 3(1), 93-102. Lien externe
Thibeault, C., Savaria, Y., & Houle, J.-L. (1990). Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits. (Rapport technique n° EPM-RT-90-11). Accès restreint
Thibeault, C., Savaria, Y., & Houle, J.-L. (1988). Yield formula for two-level hierarchical fault-tolerant integrated circuit. (Rapport technique n° EPM-RT-88-25). Accès restreint
