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Benyoussef, M., Thibeault, C., & Savaria, Y. (2019, May). A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). External link
Bouanen, S., Thibeault, C., Savaria, Y., Tremblay, J.-P., & Zhu, G. (2013, October). Fault tolerant smart transducer interface for safety-critical avionics applications [Paper]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. External link
Chureau, A., Savaria, Y., Boland, J.-F., Zilic, Z., Thibeault, C., & Gagnon, F. (2006, June). Building heterogeneous functional prototypes using articulated interfaces [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link
Darvishi, M., Audet, Y., Blaquiere, Y., Thibeault, C., & Pichette, S. (2019). On the susceptibility of SRAM-Based FPGA routing network to delay changes induced by ionizing radiation. IEEE Transactions on Nuclear Science, 66(3), 643-654. External link
Darvishi, M., Audet, Y., Blaquiere, Y., Thibeault, C., Pichette, S., & Tazi, F. Z. (2014). Circuit level modeling of extra combinational delays in SRAM-based FPGAs due to transient ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3535-3542. External link
El Mustapha Ait Yakoub, M., Sawan, M., & Thibeault, C. (2009, June). A neuromimetic ultra low-power ADC for bio-sensing applications [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link
Fiorentino, M., Thibeault, C., & Savaria, Y. (2021). Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow. IET Computers & Digital Techniques, 15(6), 409-426. Available
Fiorentino, M., Thibeault, C., Savaria, Y., Gagnon, F., Awad, T., Morrissey, D., & Laurence, M. (2019, May). AnARM: a 28nm energy efficient ARM processor based on Octasic asynchronous technology [Paper]. 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2019), Hirosaki, Japan. External link
Fiorentino, M., Savaria, Y., & Thibeault, C. (2017, June). FPGA implementation of Token-based Self-timed processors: A case study [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link
Fiorentino, M., Savaria, Y., Thibeault, C., & Gervais, P. (2016, May). A practical design method for prototyping self-timed processors using FPGAs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. External link
Fiorentino, M., Al-Terkawi, O., Savaria, Y., & Thibeault, C. (2015, June). Self-timed circuits FPGA implementation flow [Paper]. 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). External link
Gagnon, F., Savaria, Y., Dumais, P., Ammari, M. L., & Thibeault, C. (2010). Multiequalizer unit used for telecommunications has decision unit, which receives corresponding synchronized signals and choose one synchronized signal that matches with predetermined transmission performance criterion signal. (Patent no. US7693490). External link
Gagnon, Y., Savaria, Y., Meunier, M., & Thibeault, C. (1997, October). Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model [Paper]. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1997), Paris, Fr. External link
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2020). Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. Journal of Electronic Testing-Theory and Applications, 35(6), 823-838. External link
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2020). Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(3), 764-776. External link
Hasib, O. A.-T., Crepeau, D., Awad, T., Dulipovici, A., Savaria, Y., & Thibeault, C. (2018, April). Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits [Paper]. 36th IEEE VLSI Test Symposium (VTS 2018), Los Alamitos, CA (6 pages). External link
Hasib, O. A.-T., Savaria, Y., & Thibeault, C. (2016, April). WeSPer: a flexible small delay defect quality metric [Paper]. 34th IEEE VLSI Test Symposium (VTS 2016), Las Vegas, Nevada (6 pages). External link
Hoque, K. A., Mohamed, O. A., Savaria, Y., & Thibeault, C. (2014, October). Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications [Paper]. 12th ACM/IEEE International Conference on Methods and Models for System Design (MEMOCODE 2014), Lausanne, Switzerland. External link
Hoque, K. A., Ait Mohamed, O., Savaria, Y., & Thibeault, C. (2013, October). Early analysis of soft error effects for aerospace applications using probabilistic model checking [Paper]. 2nd International Workshop of Formal Techniques for Safety-Critical Systems (FTSCS 2013), Queenstown, New Zealand. External link
Hobeika, C., Pichette, S., Ghodbane, A., Thibeault, C., Audet, Y., Boland, J.-F., & Saad, M. (2013). Flight control fault models based on SEU emulation. SAE International Journal of Aerospace, 6(2), 643-649. External link
Joliveau, M., Giard, P., Gendreau, M., Gagnon, F., & Thibeault, C. (2011, June). Design of low complexity multiplierless digital filters with optimized free structure using a population-based metaheuristic [Paper]. International Symposium on Signals, Circuits and Systems, ISSCS 2011, Iasi, Romania. External link
Joliveau, M., Gendreau, M., Gagnon, F., & Thibeault, C. (2011, August). Low complexity low power non-recursive digital filters with unconstrained topology [Paper]. 20th European Conference on Circuit Theory and Design, ECCTD 2011, Linkoping, Sweden. External link
Leduc-Primeau, F., Raymond, A. J., Giard, P., Cushon, K., Thibeault, C., & Gross, W. J. (2012, October). High-throughput LDPC decoding using the RHS algorithm [Paper]. Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany (6 pages). External link
Monté-Genest, G., Antaki, B., Patenaude, S., Savaria, Y., Thibeault, C., & Trouborst, P. (2001, April). Tools for the characterization of bipolar CML testability [Paper]. 19th IEEE VLSI Test Symposium (VTS 2001), Marina Del Rey, CA, USA. External link
Prieur, D., Granger, E., Savaria, Y., & Thibeault, C. (2016). Efficient identification of faces in video streams using low-power multi-core devices. In Handbook of pattern recognition and computer vision (5th ed.). External link
Sahraii, N., Savaria, Y., Thibeault, C., & Gagnon, F. (2008, June). Scheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link
Tazi, F. Z., Thibeault, C., & Savaria, Y. (2016, May). Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA [Paper]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2016), Vancouver, British Columbia (5 pages). External link
Tazi, F. Z., Thibeault, C., Savaria, Y., Pichette, S., & Audet, Y. (2014). On extra delays affecting I/O blocks of an SRAM-based FPGA due to ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3138-3145. External link
Tremblay, J.-P., Savaria, Y., Zhu, G., Thibeault, C., & Bouanen, S. (2013, October). A hardware prototype for integration, test and validation of avionic networks [Paper]. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA. External link
Thibeault, C., Hariri, Y., Hasan, S. R., Hobeika, C., Savaria, Y., Audet, Y., & Tazi, F. Z. (2013). A library-based early soft error sensitivity analysis technique for SRAM-based FPGA design. Journal of Electronic Testing: Theory and Applications, 29(4), 457-471. External link
Trentin, D., Savaria, Y., Zhu, G., & Thibeault, C. (2012, October). An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization [Paper]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ. Published in SAE International Journal of Aerospace, 5(1). External link
Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquière, Y., Moupfouma, F., & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65. External link
Tremblay, J.-P., Savaria, Y., Zhu, G., Thibeault, C., & Bouanen, S. (2012, October). A System Architecture for Smart Sensors Integration in Avionics Applications [Paper]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ. Published in SAE International Journal of Aerospace, 5(1). External link
Tremblay, J.-P., Savaria, Y., Thibeault, C., & Mbaye, M. (2008, October). Improving resource utilization in an multiple asynchronous ALU DSP architecture [Paper]. 1st Microsystems and Nanoelectronics Research Conference. External link
Thibeault, C., Savaria, Y., & Houle, J.-L. (1994). A fast method to evaluate the optimum number of spares in defect-tolerant integrated-circuits. IEEE Transactions on Computers, 43(6), 687-697. External link
Thibeault, C., Savaria, Y., & Houle, J.-L. (1992). Test quality of hierarchical defect-tolerant integrated circuits. Journal of Electronic Testing, 3(1), 93-102. External link
Thibeault, C., Savaria, Y., & Houle, J.-L. (1990). Equivalence proofs of some yield modeling methods for defect-tolerant integrated circuits. (Technical Report n° EPM-RT-90-11). Restricted access
Thibeault, C., Savaria, Y., & Houle, J.-L. (1988). Yield formula for two-level hierarchical fault-tolerant integrated circuit. (Technical Report n° EPM-RT-88-25). Restricted access
