Mohamed Soufi, Steve Rochon, Yvon Savaria
and Bozena Kaminska
Paper (1996)
An external link is available for this item
| Additional Information: | Nom historique du département: Département de génie électrique et de génie informatique |
|---|---|
| Department: |
Department of Electrical Engineering Department of Computer Engineering and Software Engineering |
| PolyPublie URL: | https://publications.polymtl.ca/30861/ |
| Conference Title: | 14th IEEE VLSI Test Symposium |
| Conference Location: | Princeton, NJ, USA |
| Conference Date(s): | 1996-04-28 - 1996-05-01 |
| Publisher: | IEEE |
| DOI: | 10.1109/vtest.1996.510880 |
| Official URL: | https://doi.org/10.1109/vtest.1996.510880 |
| Date Deposited: | 18 Apr 2023 15:24 |
| Last Modified: | 25 Sep 2024 16:12 |
| Cite in APA 7: | Soufi, M., Rochon, S., Savaria, Y., & Kaminska, B. (1996, April). Design and performance of CMOS TSPC cells for high speed pseudo random testing [Paper]. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. https://doi.org/10.1109/vtest.1996.510880 |
|---|---|
Statistics
Dimensions
Repository Staff Only
|
View Item |
