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Abderrahman, A., Cerny, E., & Kamińska, B. (1999). Worst Case Tolerance Analysis and Clp-Based Multifrequency Test Generation for Analog Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(3), 332-345. Lien externe
Arabi, K., & Kamińska, B. (1998). Design for Testability of Embedded Integrated Operational Amplifiers. IEEE Journal of Solid-State Circuits, 33(4), 573-581. Lien externe
Arabi, K., Kamińska, B., & Sawan, M. (1998). On Chip Testing Data Converters Using Static Parameters. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(3), 409-419. Lien externe
Abderrahman, A., Cerny, E., & Kamińska, B. (avril 1997). CLP-based multifrequency test generation for analog circuits [Communication écrite]. 1997 15th VLSI Test Symposium, Monterey, CA, USA. Lien externe
Arabi, K., & Kamińska, B. (mars 1997). Efficient and accurate testing of analog-to-digital converters using oscillation-test method [Communication écrite]. 1997 European Design & Test Conference, Paris, Fr. Lien externe
Arabi, K., & Kamińska, B. (avril 1997). Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology [Communication écrite]. 15th IEEE VLSI Test Symposium, Monterey, CA, USA. Lien externe
Aourid, S. M., & Kamińska, B. (1997). Static Test Vector Compaction by the Set Covering Problem. (Rapport technique n° 1034). Non disponible
Arabi, K., & Kamińska, B. (1997). Testing analog and mixed-signal integrated circuits using oscillation-test method. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 16(7), 745-753. Lien externe
Abderrahman, A., Savaria, Y., & Kamińska, B. (1996). Analyse, estimation et réduction du bruit de commutation simultanée. [Analysis, estimation and reduction of simultaneous switching noise]. Canadian Journal of Electrical and Computer Engineering, 21(4), 133-143. Lien externe
Arabi, K., Kamińska, B., & Rzeszut, J. (1996). BIST for D/A and A/D converters. IEEE Design & Test of Computers, 13(4), 40-49. Lien externe
Arabi, K., Kamińska, B., & Sunter, S. (octobre 1996). Design for testability of integrated operational amplifiers using oscillation-test strategy [Communication écrite]. 1996 International Conference on Computer Design, ICCD'96, Austin, TX, USA. Lien externe
Aourid, S. M., & Kamińska, B. (1996). Minimization of the 0-1 linear-programming problem under linear constraints by using neural networks - synthesis and analysis. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(5), 421-425. Lien externe
Arabi, K., & Kamińska, B. (octobre 1996). A new technique to monitor the electrode and lead failures in implantable microstimulators and sensors [Communication écrite]. 1996 18th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Amsterdam, Netherlands. Lien externe
Abderrahman, A., Cerny, E., & Kamińska, B. (1996). Optimization-based multifrequency test generation for analog circuits. Journal of Electronic Testing: Theory and Applications (JETTA), 9(1-2), 59-73. Lien externe
Arabi, K., & Kamińska, B. (avril 1996). Oscillation-test strategy for analog and mixed-signal integrated circuits [Communication écrite]. 1996 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe
Arabi, K., & Kamińska, B. (octobre 1996). A practical and low-cost test method to design reliable implantable systems [Communication écrite]. 1996 18th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Amsterdam, Netherlands. Lien externe
Ayari, B., Ben Hamida, N., & Kamińska, B. (mars 1995). Automatic test vector generation for mixed-signal circuits [Communication écrite]. European Conference on Design and Test (EDTC 1995), Paris, France. Lien externe
Ayari, B., & Kamińska, B. (avril 1995). BDD_FTEST: fast, backtrack-free test generator based on binary decision diagram representation [Communication écrite]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. Lien externe
Ayari, B., & Kamińska, B. (1995). CYCLOGEN: Automatic, functional-level test generator based on the cyclomatic complexity measure and on the ROBDD representation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(7), 446-452. Lien externe
Assi, A., & Kamińska, B. (mars 1995). Modeling of communication protocols in VHDL [Communication écrite]. 5th Great Lakes Symposium on VLSI, Buffalo, NY, USA. Lien externe
Aourid, S. M., Do, X.-D., & Kamińska, B. (novembre 1995). Penalty formulation for 0-1 linear programming problem: a neural network approach [Communication écrite]. IEEE International Conference on Neural Networks (ICNN 1995), Perth, WA, Australia. Lien externe
Arabi, K., Kamińska, B., & Rzeszut, J. (novembre 1994). Built-in self-test approach for medium to high-resolution digital-to-analog converters [Communication écrite]. 3rd Asian Test Symposium, Nara, Japon. Lien externe
Abderrahman, A., Kamińska, B., & Savaria, Y. (février 1994). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits [Communication écrite]. European Design and Test Conference, Paris, Fr. Lien externe
Amellal, S., & Kamińska, B. (1994). Functional synthesis of digital systems with TASS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(5), 537-552. Lien externe
Aourid, S. M., & Kamińska, B. (juin 1994). Neural networks for the set covering problem: An application to the test vector compaction [Communication écrite]. 1994 IEEE International Conference on Neural Networks, Orlando, FL, USA. Lien externe
Arabi, K., Kamińska, B., & Rzeszut, J. (novembre 1994). New built-in self-test approach for digital-to-analog and analog-to-digital converters [Communication écrite]. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, USA. Publié dans IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Lien externe
Ayari, B., & Kamińska, B. (1994). New dynamic test vector compaction for automatic test pattern generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(3), 353-358. Lien externe
Amellal, S., & Kamińska, B. (février 1993). Scheduling algorithm in data path synthesis using the Tabu search technique [Communication écrite]. European Conference on Design Automation (EDAC 1993), Paris, France. Lien externe
Aourid, M., Mukhedkar, D., & Kamińska, B. (juin 1992). Convergence and stability study of Hopfield's neural network for linear programming [Communication écrite]. International Joint Conference on Neural Networks (IJCNN 1992), Baltimore, MD, USA. Lien externe
Ayari, B., & Kamińska, B. (novembre 1992). Cyclogen: automatic, functional-level test generator [Communication écrite]. 1st Asian Test Symposium (ATS 1992), Hiroshima, Japan. Lien externe
Aubin, F., Slamani, M., Kamińska, B., & Robert, J.-M. (octobre 1991). Biolink: A New Myoelectric Pointing Device For interactive Computer Systems: Evaluation Of The Human Performance And Integrated Realization [Communication écrite]. Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Orlando, FL, USA. Lien externe
Boyogueno Bendé, A., Kamińska, B., & Slamani, M. (mai 2000). A preamplifier IC design for photonic links [Communication écrite]. IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century (ISCAS 2000 Geneva), Geneva, Switzerland. Lien externe
Boubezari, S., Cerny, E., Kamińska, B., & Nadeau-Dostie, B. (1999). Testability Analysis and Test-Point Insertion in Rtl Vhdl Specifications for Scan-Based Bist. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(9), 1327-1340. Lien externe
Boyogueno Bendé, A., & Kamińska, B. (septembre 1998). Broad-band low-noise preamplifier design with GaAs MESFETs for optical communication systems [Communication écrite]. URSI International Symposium on Signal, Systems, and Electronics, Pisa, Italy. Lien externe
BenHamida, N., Saab, K., Marche, D., Kamińska, B., & Quesnel, G. (octobre 1996). LIMSoft: Automated tool for design and test integration of analog circuits [Communication écrite]. 1996 IEEE International Test Conference, Washington, DC, USA. Lien externe
Boubezari, S., & Kamińska, B. (1996). New reconfigurable test vector generator for built-in self-test applications. Journal of Electronic Testing: Theory and Applications (JETTA), 8(2), 153-164. Lien externe
Belhaouane, A., Savaria, Y., & Kamińska, B. (1996). Reconstruction method for data acquisition systems with randomly distributed jitter [Communication écrite]. 2nd IEEE International Mixed Signal Testing Workshop. Non disponible
Belhaouane, A., Savaria, Y., Kamińska, B., & Massicotte, D. (1996). Reconstruction method for jitter tolerant data acquisition system. Journal of Electronic Testing: Theory and Applications, 9(1-2), 177-185. Lien externe
Ben-Hamida, N., Ayari, B., & Kamińska, B. (octobre 1996). Testing of embedded A/D converters in mixed-signal circuit [Communication écrite]. 1996 International Conference on Computer Design, ICCD'96, Austin, TX, USA. Lien externe
Bechir, A., & Kamińska, B. (avril 1995). BDD FTEST: fast, backtrack-free test generator based on binary decision diagram representation [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA. Lien externe
Boubezari, S., & Kamińska, B. (1995). Deterministic built-in self-test generator based on cellular automata structures. IEEE Transactions on Computers, 44(6), 805-816. Lien externe
Boubezari, S., & Kamińska, B. (avril 1995). Mixed deterministic and pseudorandom test vector generator based on cellular automata structures [Communication écrite]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. Lien externe
BenHamida, N., & Kamińska, B. (mai 1994). High level synthesis with testability constraints [Communication écrite]. IEEE International Symposium on Circuits and Systems - ISCAS '94, London, UK. Lien externe
BenHamida, N., & Kamińska, B. (janvier 1994). Multiple fault testing in analog circuits [Communication écrite]. 7th International Conference on VLSI Design, Calcutta, India. Lien externe
BenHamida, N., Kamińska, B., & Savaria, Y. (mai 1994). Pseudo-random vector compaction for sequential testability [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. Lien externe
Ben Hamida, N., & Kamińska, B. (1993). Multiple fault analog circuit testing by sensitivity analysis. Analog Integrated Circuits and Signal Processing, 4(3), 231-243. Lien externe
BenHamida, N., & Kamińska, B. (octobre 1993). Analog circuit testing based on sensitivity computation and new circuit modeling [Communication écrite]. International Test Conference 1993, Baltimore, MD, USA. Lien externe
Dahmani, A., Savaria, Y., & Kamińska, B. (février 1993). ML-Germinal: A new heuristic standard cell placement algorithm [Communication écrite]. European Conference on Design Automation (EDAC 1993), Paris, France. Lien externe
Dahmani, A., Savaria, Y., & Kamińska, B. (mai 1992). Standard cell placement with Dynamic Clouds method [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. Lien externe
Ehsanian, M., Kamińska, B., & Arabi, K. (1998). New on-Chip Digital Bist for Analog-to-Digital Converters. Microelectronics and reliability, 38(3), 409-420. Lien externe
Ehsanian, M., BenHamida, N., & Kamińska, B. (juin 1997). Novel A/D converter for high-resolution and high-speed applications [Communication écrite]. 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97, Hong Kong, Hong Kong. Lien externe
Ehsanian, M., & Kamińska, B. (1996). BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain. Analog Integrated Circuits and Signal Processing, 11(1), 63-71. Lien externe
Ehsanian, M., & Kamińska, B. (mai 1996). A BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Atlanta, GA, USA. Lien externe
Ehsanian, M., Kamińska, B., & Arabi, K. (avril 1996). New digital test approach for analog-to-digital converter testing [Communication écrite]. 1996 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe
Fares, M., & Kamińska, B. (mai 1994). Test strategy selection for multi-chip systems [Communication écrite]. 1994 3rd International Conference on the Economics of Design, Test, and Manufacturing, Austin, TX, USA. Lien externe
Fares, M., & Kamińska, B. (1995). FPAD: a fuzzy nonlinear programming approach to analog circuit design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(7), 785-793. Lien externe
Fares, M., & Kamińska, B. (1994). Fuzzy optimization models for analog test decisions. Journal of Electronic Testing: Theory and Applications (JETTA), 5(2-3), 299-305. Lien externe
Fares, M., & Kamińska, B. (1994). Exploring test space with fuzzy decision making. IEEE Design & Test of Computers, 11(3), 17-27. Lien externe
Fares, M., & Kamińska, B. (avril 1993). A fuzzy decision-making approach for test space exploration [Communication écrite]. 3rd European Test Conference, Rotterdam, Netherlands. Lien externe
Gagnon, M., & Kamińska, B. (novembre 1997). Optical communication channel test using BIST approaches [Communication écrite]. 1997 IEEE International Test Conference, Washington, DC, USA. Lien externe
Gadiri, A., Savaria, Y., & Kamińska, B. (septembre 1995). Optimized CMOS compatible photoreceiver [Communication écrite]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, QC, Canada. Lien externe
Hamida, N. B., & Kamińska, B. (juin 1991). A uniform testability measures representation for sequential and combinational circuits [Communication écrite]. International Symposium on Circuits and Systems (ISCAS 1991), Singapore. Lien externe
Jamoussi, M., Amellal, S., & Kamińska, B. (décembre 1998). High-level testability evaluation of TASS synthesized systems [Communication écrite]. 10th International Conference on Microelectronics (ICM 1998), Monastir, Tunisia. Lien externe
Jamoussi, M., & Kamińska, B. (janvier 1994). Data path testability evaluation via functional testability measures [Communication écrite]. 7th International Conference on VLSI Design, Calcutta, India. Lien externe
Jamoussi, M., & Kamińska, B. (février 1994). M-testability: An approach for data-path testability evaluation [Communication écrite]. European Design and Test Conference, Paris, Fr. Lien externe
Jamoussi, M., Kamińska, B., & Mukhedkar, D. (1994). Testability of one-dimensional iterative arrays using a variable testability measure. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 41(1), 82-86. Lien externe
Jamoussi, M., & Kamińska, B. (avril 1993). Controllability and observability measures for functional-level testability evaluation [Communication écrite]. 11th IEEE VLSI Test Symposium, Atlantic City, NJ, USA. Lien externe
Jamoussi, M., Kamińska, B., & Mukhedkar, D. (janvier 1992). A New variable testability measure: A concept for data-flow testability evaluation [Communication écrite]. 5th International Conference on VLSI Design (ICVD 1992), Bangalore, India. Lien externe
Kamińska, B. (1996). IEEE mixed-signal testing workshop. IEEE Design & Test of Computers, 13(3), 114-114. Non disponible
Khaled, S., Kamińska, B., Courtois, B., & Lubaszewski, M. (avril 1995). Frequency-based BIST for analog circuit testing [Communication écrite]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe
Kamińska, B., & Mheir-El-Saadi, F. (mai 1990). A framework for performance and knowledge-based control of basic designs [Communication écrite]. EURO ASIC 1990, Paris, France. Lien externe
Kamińska, B., & Savaria, Y. (août 1989). Design-for-testability using test design yield and decision theory [Communication écrite]. International Test Conference 1989, Washington, DC, USA. Lien externe
Kamińska, B., & Mheir-El-Saadi, F. (juin 1989). VLSI design in heuristic environment [Communication écrite]. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1989), Victoria, BC, Canada. Lien externe
Kamińska, B., Savaria, Y., & Houle, J.-L. (avril 1988). Design model on performance prediction for VLSI systems [Communication écrite]. System Design: Concepts, Methods and Tools (COMPEURO 1988), Brussels, Belgium. Lien externe
Lejmi, S., Kamińska, B., & Ayari, B. (avril 1995). Retiming for BIST-sequential circuits [Communication écrite]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. Lien externe
Lejmi, S., Kamińska, B., & Ayari, B. (avril 1995). Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits [Communication écrite]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe
Lejmi, S., Kamińska, B., & Ayari, B. (octobre 1995). Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits [Communication écrite]. 1995 26th International Test Conference, Washington, DC, USA. Lien externe
Lejmi, S., Kamińska, B., & Wagneur, E. (octobre 1994). Retiming for the global optimization of synchronous sequential circuits [Communication écrite]. IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA. Lien externe
Mheir-El-Saadi, F., & Kamińska, B. (1994). Automatic hierarchical delay analysis tool. Journal of Computer Science and Technology, 9(4), 349-364. Lien externe
Mheir-El-Saadi, F., & Kamińska, B. (août 1990). RC-tree delay evaluation in hierarchical environment [Communication écrite]. 33rd Midwest Symposium on Circuits and Systems (MWSCAS 1990), Calgary, AB, Canada. Lien externe
Oudghiri, H., Kamińska, B., & Rajski, J. (mai 1997). A hardware/software partitioning technique with hierarchical design space exploration [Communication écrite]. CICC 97 - Custom Integrated Circuits Conference, Santa Clara, CA, USA. Lien externe
Oudghiri, H., & Kamińska, B. (mars 1992). Global weighted scheduling and allocation algorithms [Communication écrite]. European Conference on Design Automation (EDAC 1992), Brussels, Belgium. Lien externe
Oudghiri, H., & Kamińska, B. (1991). Global weighted scheduling and allocation algorithms. (Rapport technique n° EPM-RT-91-01). Accès restreint
Oudghiri, H., & Kamińska, B. (1991). Synthèse de haut niveau : ordonnancement et allocation. (Rapport technique n° EPM-RT-91-02). Accès restreint
Rayapati, V. N., & Kamińska, B. (1997). Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation. Microelectronics and reliability, 37(5), 785-794. Lien externe
Rayapati, V. N., & Kamińska, B. (1996). Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip. IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part B, Advanced Packaging, 19(3), 605-614. Lien externe
Rzeszut, J., Kamińska, B., & Savaria, Y. (novembre 1995). New method for testing mixed analog and digital circuits [Communication écrite]. 4th Asian Test Symposium, Bangalore, India. Lien externe
Rayapati, V. N., & Kamińska, B. (1994). A dynamic reconfiguration scheme for mega bit static random access memories. Microelectronics and reliability, 34(1), 107-114. Lien externe
Rayapati, V. N., & Kamińska, B. (août 1994). Mega bit BiCMOS SRAM chip package modelling and performance analysis [Communication écrite]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, CA, USA. Lien externe
Rayapati, V. N., & Kamińska, B. (août 1994). Mega bit CMOS SRAM chip failure analysis using external electrical testing and internal contactless laser beam testing [Communication écrite]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, CA, USA. Lien externe
Rayapati, V. N., & Kamińska, B. (août 1993). Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs [Communication écrite]. IEEE International Workshop on Memory Testing (MT 1993), San Jose, CA, United states. Lien externe
Rayapati, V. N., & Kamińska, B. (octobre 1993). Multilayer interconnection model for BiCMOS SRAMs [Communication écrite]. Electrical Performance of Electronic Packaging, Monterey, CA, USA. Lien externe
Sylla, I. T., Slamani, M., Kamińska, B., Hossein, F. M., & Vincent, P. (avril 1998). Impedance mismatch and lumped capacitance effects in high frequency testing [Communication écrite]. 16th IEEE VLSI Test Symposium, Monterey, CA, USA. Lien externe
Sokolowska, E., Fortin, G., Belabbes, N., Gagnon, M., & Kamińska, B. (septembre 1998). Scalable pseudo-optical switching system for multi-protocol environment [Communication écrite]. IEEE International Conference on Electronics, Circuits, and Systems, Lisboa, Portugal. Lien externe
Sokolowska, E., Fortin, G., Belabbes, N., Gagnon, M., Roy, C., & Kamińska, B. (octobre 1997). Bidirectional Analog 8x8 Switch Matrix with Large Input Signal and Over lGHz Bandwidth [Communication écrite]. 1997 19th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, Anaheim, CA, USA. Lien externe
Sokolowska, E., Belabbes, N., & Kamińska, B. (juin 1997). Integrated analog switch matrix with large input signal and 46dB isolation at 1GHz [Communication écrite]. 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97, Hong Kong, Hong Kong. Lien externe
Sylla, I.-T., Slamani, M., Kamińska, B., & Ghannouchi, F. M. (1997). Joint design and test consideration in high frequency circuits. Microwave and Optical Technology Letters, 16(3), 132-138. Lien externe
Soufi, M., Rochon, S., Savaria, Y., & Kamińska, B. (avril 1996). Design and performance of CMOS TSPC cells for high speed pseudo random testing [Communication écrite]. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe
Slamani, M., & Kamińska, B. (1996). Fault observability analysis of analog circuits in frequency-domain. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 43(2), 134-139. Lien externe
Sokolowska, E., Belabbes, N. E., & Kamińska, B. (avril 1996). Integrated analog switch matrix with large input signal and 46dB isolation at 1 GHz [Communication écrite]. 1996 International IFIP-IEEE Conference on Broadband Communications, Montréal, Québec. Lien externe
Saab, K., Marche, D., BenHamida, N., & Kamińska, B. (1996). LIMSoft : automated tool for sensitivity analysis and test vector generation : Mixed signal & analogue IC test technology. IEE Proceedings. Circuits, Devices and Systems, 143(6), 386-392. Lien externe
Slamani, M., & Kamińska, B. (1995). Multifrequency analysis of faults in analog circuits. IEEE Design & Test of Computers, 12(2), 70-80. Lien externe
Soufi, M., Savaria, Y., & Kamińska, B. (avril 1995). On the design of at-speed testable VLSI circuits [Communication écrite]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. Lien externe
Soufi, M., Savaria, Y., & Kamińska, B. (avril 1995). On Using partial reset for pseudo-random testing [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA. Lien externe
Soufi, M., Savaria, Y., Darlay, F., & Kamińska, B. (1995). Producing reliable initialization and test of sequential circuits with pseudorandom vectors. IEEE Transactions on Computers, 44(10), 1251-1256. Lien externe
Sokolowska, E., & Kamińska, B. (octobre 1994). Application of optoelectronic techniques to high speed testing [Communication écrite]. 1994 IEEE International Test Conference, Washington, DC, USA. Lien externe
Slamani, M., Kamińska, B., & Quesnel, G. (octobre 1994). Integrated approach for analog circuit testing with a minimum number of detected parameters [Communication écrite]. 1994 IEEE International Test Conference, Washington, DC, USA. Lien externe
Slamani, M., & Kamińska, B. (avril 1994). Multifrequency testability analysis for analog circuits [Communication écrite]. 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, USA. Lien externe
Soufi, M., Savaria, Y., Kamińska, B., & Darlay, F. (1994). Producing reliable initialization and test of sequential circuits with pseudo-random vectors. (Rapport technique n° EPM-RT-94-23). Accès restreint
Slamani, M., & Kamińska, B. (novembre 1993). T-BIST: A built-in self-test for analog circuits based on parameter translation [Communication écrite]. 2nd IEEE Asian Test Symposium (ATS 1993), Beijing, China. Lien externe
Slamani, M., & Kamińska, B. (mars 1992). Testing analog circuits by sensitivity computation [Communication écrite]. European Conference on Design Automation (EDAC 1992), Brussels, Belgium. Lien externe
Savaria, Y., Youssef, M., Kamińska, B., & Koudil, M. (juin 1991). Automatic test point insertion for pseudo-random testing [Communication écrite]. International Symposium on Circuits and Systems (ISCAS 1991), Singapore. Lien externe
Saadi, F., & Kamińska, B. (février 1991). A framework for hierarchical performance analysis (of VLSI) [Communication écrite]. European Conference on Design Automation (EDAC 1991), Amsterdam, Netherlands. Lien externe
Savaria, Y., Laguë, B., & Kamińska, B. (août 1989). A pragmatic approach to the design of self-testing circuits [Communication écrite]. International Test Conference 1989, Washington, DC, USA. Lien externe
Stannard, D. H., & Kamińska, B. (septembre 1988). Detection of hard faults in a combinational circuit using budget constraints [Communication écrite]. International Test Conference 1988, Washington, DC, USA. Lien externe
Savaria, Y., & Kamińska, B. (juin 1988). Force-observe, a new design for testability approach (CMOS VLSI circuits) [Communication écrite]. International Symposium on Circuits and Systems (ISCAS 1988), Espoo, Finland. Lien externe
