 | Up a level |
Collaboration networkThis graph maps the connections between all the collaborators of {}'s publications listed on this page.
Each link represents a collaboration on the same publication. The thickness of the link represents the number of collaborations.
Use the mouse wheel or scroll gestures to zoom into the graph.
You can click on the nodes and links to highlight them and move the nodes by dragging them.
Hold down the "Ctrl" key or the "⌘" key while clicking on the nodes to open the list of this person's publications.
Word cloudA word cloud is a visual representation of the most frequently used words in a text or a set of texts. The words appear in different sizes, with the size of each word being proportional to its frequency of occurrence in the text. The more frequently a word is used, the larger it appears in the word cloud. This technique allows for a quick visualization of the most important themes and concepts in a text.
In the context of this page, the word cloud was generated from the publications of the author {}. The words in this cloud come from the titles, abstracts, and keywords of the author's articles and research papers. By analyzing this word cloud, you can get an overview of the most recurring and significant topics and research areas in the author's work.
The word cloud is a useful tool for identifying trends and main themes in a corpus of texts, thus facilitating the understanding and analysis of content in a visual and intuitive way.
Amellal, S., & Kamińska, B. (1993, May). Scheduling of a control data flow graph [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1993), Chicago, IL, USA. External link
Abderrahman, A., Cerny, E., & Kamińska, B. (1999). Worst Case Tolerance Analysis and Clp-Based Multifrequency Test Generation for Analog Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(3), 332-345. External link
Arabi, K., & Kamińska, B. (1998). Design for Testability of Embedded Integrated Operational Amplifiers. IEEE Journal of Solid-State Circuits, 33(4), 573-581. External link
Arabi, K., Kamińska, B., & Sawan, M. (1998). On Chip Testing Data Converters Using Static Parameters. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(3), 409-419. External link
Abderrahman, A., Cerny, E., & Kamińska, B. (1997, April). CLP-based multifrequency test generation for analog circuits [Paper]. 1997 15th VLSI Test Symposium, Monterey, CA, USA. External link
Arabi, K., & Kamińska, B. (1997, March). Efficient and accurate testing of analog-to-digital converters using oscillation-test method [Paper]. 1997 European Design & Test Conference, Paris, Fr. External link
Arabi, K., & Kamińska, B. (1997, April). Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology [Paper]. 15th IEEE VLSI Test Symposium, Monterey, CA, USA. External link
Aourid, S. M., & Kamińska, B. (1997). Static Test Vector Compaction by the Set Covering Problem. (Technical Report n° 1034). Unavailable
Arabi, K., & Kamińska, B. (1997). Testing analog and mixed-signal integrated circuits using oscillation-test method. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 16(7), 745-753. External link
Abderrahman, A., Savaria, Y., & Kamińska, B. (1996). Analyse, estimation et réduction du bruit de commutation simultanée. [Analysis, estimation and reduction of simultaneous switching noise]. Canadian Journal of Electrical and Computer Engineering, 21(4), 133-143. External link
Arabi, K., Kamińska, B., & Rzeszut, J. (1996). BIST for D/A and A/D converters. IEEE Design & Test of Computers, 13(4), 40-49. External link
Arabi, K., Kamińska, B., & Sunter, S. (1996, October). Design for testability of integrated operational amplifiers using oscillation-test strategy [Paper]. 1996 International Conference on Computer Design, ICCD'96, Austin, TX, USA. External link
Aourid, S. M., & Kamińska, B. (1996). Minimization of the 0-1 linear-programming problem under linear constraints by using neural networks - synthesis and analysis. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(5), 421-425. External link
Arabi, K., & Kamińska, B. (1996, October). A new technique to monitor the electrode and lead failures in implantable microstimulators and sensors [Paper]. 1996 18th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Amsterdam, Netherlands. External link
Abderrahman, A., Cerny, E., & Kamińska, B. (1996). Optimization-based multifrequency test generation for analog circuits. Journal of Electronic Testing: Theory and Applications (JETTA), 9(1-2), 59-73. External link
Arabi, K., & Kamińska, B. (1996, April). Oscillation-test strategy for analog and mixed-signal integrated circuits [Paper]. 1996 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Arabi, K., & Kamińska, B. (1996, October). A practical and low-cost test method to design reliable implantable systems [Paper]. 1996 18th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Amsterdam, Netherlands. External link
Ayari, B., Ben Hamida, N., & Kamińska, B. (1995, March). Automatic test vector generation for mixed-signal circuits [Paper]. European Conference on Design and Test (EDTC 1995), Paris, France. External link
Ayari, B., & Kamińska, B. (1995, April). BDD_FTEST: fast, backtrack-free test generator based on binary decision diagram representation [Paper]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. External link
Ayari, B., & Kamińska, B. (1995). CYCLOGEN: Automatic, functional-level test generator based on the cyclomatic complexity measure and on the ROBDD representation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(7), 446-452. External link
Assi, A., & Kamińska, B. (1995, March). Modeling of communication protocols in VHDL [Paper]. 5th Great Lakes Symposium on VLSI, Buffalo, NY, USA. External link
Aourid, S. M., Do, X.-D., & Kamińska, B. (1995, November). Penalty formulation for 0-1 linear programming problem: a neural network approach [Paper]. IEEE International Conference on Neural Networks (ICNN 1995), Perth, WA, Australia. External link
Arabi, K., Kamińska, B., & Rzeszut, J. (1994, November). Built-in self-test approach for medium to high-resolution digital-to-analog converters [Paper]. 3rd Asian Test Symposium, Nara, Japon. External link
Abderrahman, A., Kamińska, B., & Savaria, Y. (1994, February). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits [Paper]. European Design and Test Conference, Paris, Fr. External link
Amellal, S., & Kamińska, B. (1994). Functional synthesis of digital systems with TASS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(5), 537-552. External link
Aourid, S. M., & Kamińska, B. (1994, June). Neural networks for the set covering problem: An application to the test vector compaction [Paper]. 1994 IEEE International Conference on Neural Networks, Orlando, FL, USA. External link
Arabi, K., Kamińska, B., & Rzeszut, J. (1994, November). New built-in self-test approach for digital-to-analog and analog-to-digital converters [Paper]. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, USA. Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. External link
Ayari, B., & Kamińska, B. (1994). New dynamic test vector compaction for automatic test pattern generation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 13(3), 353-358. External link
Amellal, S., & Kamińska, B. (1993, February). Scheduling algorithm in data path synthesis using the Tabu search technique [Paper]. European Conference on Design Automation (EDAC 1993), Paris, France. External link
Aourid, M., Mukhedkar, D., & Kamińska, B. (1992, June). Convergence and stability study of Hopfield's neural network for linear programming [Paper]. International Joint Conference on Neural Networks (IJCNN 1992), Baltimore, MD, USA. External link
Ayari, B., & Kamińska, B. (1992, November). Cyclogen: automatic, functional-level test generator [Paper]. 1st Asian Test Symposium (ATS 1992), Hiroshima, Japan. External link
Aubin, F., Slamani, M., Kamińska, B., & Robert, J.-M. (1991, October). Biolink: A New Myoelectric Pointing Device For interactive Computer Systems: Evaluation Of The Human Performance And Integrated Realization [Paper]. Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Orlando, FL, USA. External link
Boubezari, S., & Kamińska, B. (1993, November). Cellular Automata Synthesis Based On Precomputed Test Vectors For Built-in Self-test [Paper]. International Conference on Computer Aided Design (ICCAD 1993), Santa Clara, CA, USA. External link
Ben Hamida, N., Kamińska, B., & Savaria, Y. (1993, May). Initiability: A Measure of Sequential Testability [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1993), Chicago, IL, USA. External link
Boyogueno Bendé, A., Kamińska, B., & Slamani, M. (2000, May). A preamplifier IC design for photonic links [Paper]. IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century (ISCAS 2000 Geneva), Geneva, Switzerland. External link
Boubezari, S., Cerny, E., Kamińska, B., & Nadeau-Dostie, B. (1999). Testability Analysis and Test-Point Insertion in Rtl Vhdl Specifications for Scan-Based Bist. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(9), 1327-1340. External link
Boyogueno Bendé, A., & Kamińska, B. (1998, September). Broad-band low-noise preamplifier design with GaAs MESFETs for optical communication systems [Paper]. URSI International Symposium on Signal, Systems, and Electronics, Pisa, Italy. External link
BenHamida, N., Saab, K., Marche, D., Kamińska, B., & Quesnel, G. (1996, October). LIMSoft: Automated tool for design and test integration of analog circuits [Paper]. 1996 IEEE International Test Conference, Washington, DC, USA. External link
Boubezari, S., & Kamińska, B. (1996). New reconfigurable test vector generator for built-in self-test applications. Journal of Electronic Testing: Theory and Applications (JETTA), 8(2), 153-164. External link
Belhaouane, A., Savaria, Y., & Kamińska, B. (1996). Reconstruction method for data acquisition systems with randomly distributed jitter [Paper]. 2nd IEEE International Mixed Signal Testing Workshop. Unavailable
Belhaouane, A., Savaria, Y., Kamińska, B., & Massicotte, D. (1996). Reconstruction method for jitter tolerant data acquisition system. Journal of Electronic Testing: Theory and Applications, 9(1-2), 177-185. External link
Ben-Hamida, N., Ayari, B., & Kamińska, B. (1996, October). Testing of embedded A/D converters in mixed-signal circuit [Paper]. 1996 International Conference on Computer Design, ICCD'96, Austin, TX, USA. External link
Bechir, A., & Kamińska, B. (1995, April). BDD FTEST: fast, backtrack-free test generator based on binary decision diagram representation [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA. External link
Boubezari, S., & Kamińska, B. (1995). Deterministic built-in self-test generator based on cellular automata structures. IEEE Transactions on Computers, 44(6), 805-816. External link
Boubezari, S., & Kamińska, B. (1995, April). Mixed deterministic and pseudorandom test vector generator based on cellular automata structures [Paper]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. External link
BenHamida, N., & Kamińska, B. (1994, May). High level synthesis with testability constraints [Paper]. IEEE International Symposium on Circuits and Systems - ISCAS '94, London, UK. External link
BenHamida, N., & Kamińska, B. (1994, January). Multiple fault testing in analog circuits [Paper]. 7th International Conference on VLSI Design, Calcutta, India. External link
BenHamida, N., Kamińska, B., & Savaria, Y. (1994, May). Pseudo-random vector compaction for sequential testability [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. External link
Ben Hamida, N., & Kamińska, B. (1993). Multiple fault analog circuit testing by sensitivity analysis. Analog Integrated Circuits and Signal Processing, 4(3), 231-243. External link
BenHamida, N., & Kamińska, B. (1993, October). Analog circuit testing based on sensitivity computation and new circuit modeling [Paper]. International Test Conference 1993, Baltimore, MD, USA. External link
Dahmani, A., Savaria, Y., & Kamińska, B. (1993, February). ML-Germinal: A new heuristic standard cell placement algorithm [Paper]. European Conference on Design Automation (EDAC 1993), Paris, France. External link
Dahmani, A., Savaria, Y., & Kamińska, B. (1992, May). Standard cell placement with Dynamic Clouds method [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1992), San Diego, CA, United states. External link
Ehsanian, M., Kamińska, B., & Arabi, K. (1998). New on-Chip Digital Bist for Analog-to-Digital Converters. Microelectronics and reliability, 38(3), 409-420. External link
Ehsanian, M., BenHamida, N., & Kamińska, B. (1997, June). Novel A/D converter for high-resolution and high-speed applications [Paper]. 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97, Hong Kong, Hong Kong. External link
Ehsanian, M., & Kamińska, B. (1996). BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain. Analog Integrated Circuits and Signal Processing, 11(1), 63-71. External link
Ehsanian, M., & Kamińska, B. (1996, May). A BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Atlanta, GA, USA. External link
Ehsanian, M., Kamińska, B., & Arabi, K. (1996, April). New digital test approach for analog-to-digital converter testing [Paper]. 1996 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Fares, M., & Kamińska, B. (1994, May). Test strategy selection for multi-chip systems [Paper]. 1994 3rd International Conference on the Economics of Design, Test, and Manufacturing, Austin, TX, USA. External link
Fares, M., & Kamińska, B. (1995). FPAD: a fuzzy nonlinear programming approach to analog circuit design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(7), 785-793. External link
Fares, M., & Kamińska, B. (1994). Fuzzy optimization models for analog test decisions. Journal of Electronic Testing: Theory and Applications (JETTA), 5(2-3), 299-305. External link
Fares, M., & Kamińska, B. (1994). Exploring test space with fuzzy decision making. IEEE Design & Test of Computers, 11(3), 17-27. External link
Fares, M., & Kamińska, B. (1993, April). A fuzzy decision-making approach for test space exploration [Paper]. 3rd European Test Conference, Rotterdam, Netherlands. External link
Gagnon, M., & Kamińska, B. (1997, November). Optical communication channel test using BIST approaches [Paper]. 1997 IEEE International Test Conference, Washington, DC, USA. External link
Gadiri, A., Savaria, Y., & Kamińska, B. (1995, September). Optimized CMOS compatible photoreceiver [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, QC, Canada. External link
Hamida, N. B., & Kamińska, B. (1991, June). A uniform testability measures representation for sequential and combinational circuits [Paper]. International Symposium on Circuits and Systems (ISCAS 1991), Singapore. External link
Jamoussi, M., & Kamińska, B. (1993, May). A functional-level testability evaluation using a new M-testability approach [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1993), Chicago, IL, USA. External link
Jamoussi, M., Amellal, S., & Kamińska, B. (1998, December). High-level testability evaluation of TASS synthesized systems [Paper]. 10th International Conference on Microelectronics (ICM 1998), Monastir, Tunisia. External link
Jamoussi, M., & Kamińska, B. (1994, January). Data path testability evaluation via functional testability measures [Paper]. 7th International Conference on VLSI Design, Calcutta, India. External link
Jamoussi, M., & Kamińska, B. (1994, February). M-testability: An approach for data-path testability evaluation [Paper]. European Design and Test Conference, Paris, Fr. External link
Jamoussi, M., Kamińska, B., & Mukhedkar, D. (1994). Testability of one-dimensional iterative arrays using a variable testability measure. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 41(1), 82-86. External link
Jamoussi, M., & Kamińska, B. (1993, April). Controllability and observability measures for functional-level testability evaluation [Paper]. 11th IEEE VLSI Test Symposium, Atlantic City, NJ, USA. External link
Jamoussi, M., Kamińska, B., & Mukhedkar, D. (1992, January). A New variable testability measure: A concept for data-flow testability evaluation [Paper]. 5th International Conference on VLSI Design (ICVD 1992), Bangalore, India. External link
Kamińska, B. (1996). IEEE mixed-signal testing workshop. IEEE Design & Test of Computers, 13(3), 114-114. Unavailable
Khaled, S., Kamińska, B., Courtois, B., & Lubaszewski, M. (1995, April). Frequency-based BIST for analog circuit testing [Paper]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Kamińska, B., & Mheir-El-Saadi, F. (1990, May). A framework for performance and knowledge-based control of basic designs [Paper]. EURO ASIC 1990, Paris, France. External link
Kamińska, B., & Savaria, Y. (1989, August). Design-for-testability using test design yield and decision theory [Paper]. International Test Conference 1989, Washington, DC, USA. External link
Kamińska, B., & Mheir-El-Saadi, F. (1989, June). VLSI design in heuristic environment [Paper]. IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1989), Victoria, BC, Canada. External link
Kamińska, B., Savaria, Y., & Houle, J.-L. (1988, April). Design model on performance prediction for VLSI systems [Paper]. System Design: Concepts, Methods and Tools (COMPEURO 1988), Brussels, Belgium. External link
Lejmi, S., Kamińska, B., & Wagneur, É. (1993, May). Resynthesis and retiming of synchronous sequential circuits [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1993), Chicago, IL, USA. External link
Lejmi, S., Kamińska, B., & Ayari, B. (1995, April). Retiming for BIST-sequential circuits [Paper]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. External link
Lejmi, S., Kamińska, B., & Ayari, B. (1995, April). Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits [Paper]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Lejmi, S., Kamińska, B., & Ayari, B. (1995, October). Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits [Paper]. 1995 26th International Test Conference, Washington, DC, USA. External link
Lejmi, S., Kamińska, B., & Wagneur, E. (1994, October). Retiming for the global optimization of synchronous sequential circuits [Paper]. IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA. External link
Mheir-El-Saadi, F., & Kamińska, B. (1994). Automatic hierarchical delay analysis tool. Journal of Computer Science and Technology, 9(4), 349-364. External link
Mheir-El-Saadi, F., & Kamińska, B. (1990, August). RC-tree delay evaluation in hierarchical environment [Paper]. 33rd Midwest Symposium on Circuits and Systems (MWSCAS 1990), Calgary, AB, Canada. External link
Oudghiri, H., Kamińska, B., & Rajski, J. (1997, May). A hardware/software partitioning technique with hierarchical design space exploration [Paper]. CICC 97 - Custom Integrated Circuits Conference, Santa Clara, CA, USA. External link
Oudghiri, H., & Kamińska, B. (1992, March). Global weighted scheduling and allocation algorithms [Paper]. European Conference on Design Automation (EDAC 1992), Brussels, Belgium. External link
Oudghiri, H., & Kamińska, B. (1991). Global weighted scheduling and allocation algorithms. (Technical Report n° EPM-RT-91-01). Restricted access
Oudghiri, H., & Kamińska, B. (1991). Synthèse de haut niveau : ordonnancement et allocation. (Technical Report n° EPM-RT-91-02). Restricted access
Rayapati, V. N., & Kamińska, B. (1997). Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation. Microelectronics and reliability, 37(5), 785-794. External link
Rayapati, V. N., & Kamińska, B. (1996). Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip. IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part B, Advanced Packaging, 19(3), 605-614. External link
Rzeszut, J., Kamińska, B., & Savaria, Y. (1995, November). New method for testing mixed analog and digital circuits [Paper]. 4th Asian Test Symposium, Bangalore, India. External link
Rayapati, V. N., & Kamińska, B. (1994). A dynamic reconfiguration scheme for mega bit static random access memories. Microelectronics and reliability, 34(1), 107-114. External link
Rayapati, V. N., & Kamińska, B. (1994, August). Mega bit BiCMOS SRAM chip package modelling and performance analysis [Paper]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, CA, USA. External link
Rayapati, V. N., & Kamińska, B. (1994, August). Mega bit CMOS SRAM chip failure analysis using external electrical testing and internal contactless laser beam testing [Paper]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, CA, USA. External link
Rayapati, V. N., & Kamińska, B. (1993, August). Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs [Paper]. IEEE International Workshop on Memory Testing (MT 1993), San Jose, CA, United states. External link
Rayapati, V. N., & Kamińska, B. (1993, October). Multilayer interconnection model for BiCMOS SRAMs [Paper]. Electrical Performance of Electronic Packaging, Monterey, CA, USA. External link
Sylla, I. T., Slamani, M., Kamińska, B., Hossein, F. M., & Vincent, P. (1998, April). Impedance mismatch and lumped capacitance effects in high frequency testing [Paper]. 16th IEEE VLSI Test Symposium, Monterey, CA, USA. External link
Sokolowska, E., Fortin, G., Belabbes, N., Gagnon, M., & Kamińska, B. (1998, September). Scalable pseudo-optical switching system for multi-protocol environment [Paper]. IEEE International Conference on Electronics, Circuits, and Systems, Lisboa, Portugal. External link
Sokolowska, E., Fortin, G., Belabbes, N., Gagnon, M., Roy, C., & Kamińska, B. (1997, October). Bidirectional Analog 8x8 Switch Matrix with Large Input Signal and Over lGHz Bandwidth [Paper]. 1997 19th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, Anaheim, CA, USA. External link
Sokolowska, E., Belabbes, N., & Kamińska, B. (1997, June). Integrated analog switch matrix with large input signal and 46dB isolation at 1GHz [Paper]. 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97, Hong Kong, Hong Kong. External link
Sylla, I.-T., Slamani, M., Kamińska, B., & Ghannouchi, F. M. (1997). Joint design and test consideration in high frequency circuits. Microwave and Optical Technology Letters, 16(3), 132-138. External link
Soufi, M., Rochon, S., Savaria, Y., & Kamińska, B. (1996, April). Design and performance of CMOS TSPC cells for high speed pseudo random testing [Paper]. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Slamani, M., & Kamińska, B. (1996). Fault observability analysis of analog circuits in frequency-domain. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 43(2), 134-139. External link
Sokolowska, E., Belabbes, N. E., & Kamińska, B. (1996, April). Integrated analog switch matrix with large input signal and 46dB isolation at 1 GHz [Paper]. 1996 International IFIP-IEEE Conference on Broadband Communications, Montréal, Québec. External link
Saab, K., Marche, D., BenHamida, N., & Kamińska, B. (1996). LIMSoft : automated tool for sensitivity analysis and test vector generation : Mixed signal & analogue IC test technology. IEE Proceedings. Circuits, Devices and Systems, 143(6), 386-392. External link
Slamani, M., & Kamińska, B. (1995). Multifrequency analysis of faults in analog circuits. IEEE Design & Test of Computers, 12(2), 70-80. External link
Soufi, M., Savaria, Y., & Kamińska, B. (1995, April). On the design of at-speed testable VLSI circuits [Paper]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Soufi, M., Savaria, Y., & Kamińska, B. (1995, April). On Using partial reset for pseudo-random testing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA. External link
Soufi, M., Savaria, Y., Darlay, F., & Kamińska, B. (1995). Producing reliable initialization and test of sequential circuits with pseudorandom vectors. IEEE Transactions on Computers, 44(10), 1251-1256. External link
Sokolowska, E., & Kamińska, B. (1994, October). Application of optoelectronic techniques to high speed testing [Paper]. 1994 IEEE International Test Conference, Washington, DC, USA. External link
Slamani, M., Kamińska, B., & Quesnel, G. (1994, October). Integrated approach for analog circuit testing with a minimum number of detected parameters [Paper]. 1994 IEEE International Test Conference, Washington, DC, USA. External link
Slamani, M., & Kamińska, B. (1994, April). Multifrequency testability analysis for analog circuits [Paper]. 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, USA. External link
Soufi, M., Savaria, Y., Kamińska, B., & Darlay, F. (1994). Producing reliable initialization and test of sequential circuits with pseudo-random vectors. (Technical Report n° EPM-RT-94-23). Restricted access
Slamani, M., & Kamińska, B. (1993, November). T-BIST: A built-in self-test for analog circuits based on parameter translation [Paper]. 2nd IEEE Asian Test Symposium (ATS 1993), Beijing, China. External link
Slamani, M., & Kamińska, B. (1992, March). Testing analog circuits by sensitivity computation [Paper]. European Conference on Design Automation (EDAC 1992), Brussels, Belgium. External link
Savaria, Y., Youssef, M., Kamińska, B., & Koudil, M. (1991, June). Automatic test point insertion for pseudo-random testing [Paper]. International Symposium on Circuits and Systems (ISCAS 1991), Singapore. External link
Saadi, F., & Kamińska, B. (1991, February). A framework for hierarchical performance analysis (of VLSI) [Paper]. European Conference on Design Automation (EDAC 1991), Amsterdam, Netherlands. External link
Savaria, Y., Laguë, B., & Kamińska, B. (1989, August). A pragmatic approach to the design of self-testing circuits [Paper]. International Test Conference 1989, Washington, DC, USA. External link
Stannard, D. H., & Kamińska, B. (1988, September). Detection of hard faults in a combinational circuit using budget constraints [Paper]. International Test Conference 1988, Washington, DC, USA. External link
Savaria, Y., & Kamińska, B. (1988, June). Force-observe, a new design for testability approach (CMOS VLSI circuits) [Paper]. International Symposium on Circuits and Systems (ISCAS 1988), Espoo, Finland. External link
