Venkatapathi N. Rayapati and Bozena Kaminska
Paper (1994)
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| Additional Information: | Nom historique du département: Département de génie électrique et de génie informatique |
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| Department: |
Department of Electrical Engineering Department of Computer Engineering and Software Engineering |
| PolyPublie URL: | https://publications.polymtl.ca/32924/ |
| Conference Title: | IEEE International Workshop on Memory Technology, Design, and Testing |
| Conference Location: | San Jose, Cal, USA |
| Conference Date(s): | 1994-08-08 - 1994-08-09 |
| Publisher: | Institute of Electrical and Electronics Engineers |
| DOI: | 10.1109/mtdt.1994.397204 |
| Official URL: | https://doi.org/10.1109/mtdt.1994.397204 |
| Date Deposited: | 18 Apr 2023 15:25 |
| Last Modified: | 08 Apr 2025 06:53 |
| Cite in APA 7: | Rayapati, V. N., & Kaminska, B. (1994, August). Mega bit BiCMOS SRAM chip package modelling and performance analysis [Paper]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, Cal, USA. https://doi.org/10.1109/mtdt.1994.397204 |
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