Documents dont l'auteur est "Rayapati, Venkatapathi N."

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Rayapati, V. N., & Kaminska, B. (1996). Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip. IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part B, Advanced Packaging, 19(3), 605-614. Lien externe

Rayapati, V. N., & Kaminska, B. (1994). A dynamic reconfiguration scheme for mega bit static random access memories. Microelectronics and reliability, 34(1), 107-114. Lien externe

Rayapati, V. N., & Kaminska, B. (août 1994). Mega bit BiCMOS SRAM chip package modelling and performance analysis [Communication écrite]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, Cal, USA. Lien externe

Rayapati, V. N., & Kaminska, B. (août 1994). Mega bit CMOS SRAM chip failure analysis using external electrical testing and internal contactless laser beam testing [Communication écrite]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, Cal, USA. Lien externe

Rayapati, V. N., & Kaminska, B. (août 1993). Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs [Communication écrite]. IEEE International Workshop on Memory Testing (MT 1993), San Jose, CA, United states. Lien externe