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Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip

Venkatapathi N. Rayapati and Bozena Kaminska

Article (1996)

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Additional Information: Nom historique du département: Département de génie électrique et de génie informatique
Department: Department of Electrical Engineering
Department of Computer Engineering and Software Engineering
PolyPublie URL: https://publications.polymtl.ca/30932/
Journal Title: IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part B, Advanced Packaging (vol. 19, no. 3)
Publisher: IEEE
DOI: 10.1109/96.533903
Official URL: https://doi.org/10.1109/96.533903
Date Deposited: 18 Apr 2023 15:24
Last Modified: 05 Apr 2024 11:20
Cite in APA 7: Rayapati, V. N., & Kaminska, B. (1996). Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip. IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part B, Advanced Packaging, 19(3), 605-614. https://doi.org/10.1109/96.533903

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