Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip

Venkatapathi N. Rayapati and Bozena Kaminska

Article (1996)

An external link is available for this item

Additional Information:	Nom historique du département: Département de génie électrique et de génie informatique
Department:	Department of Electrical Engineering Department of Computer Engineering and Software Engineering
PolyPublie URL:	https://publications.polymtl.ca/30932/
Journal Title:	IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part B, Advanced Packaging (vol. 19, no. 3)
Publisher:	IEEE
DOI:	10.1109/96.533903
Official URL:	https://doi.org/10.1109/96.533903
Date Deposited:	18 Apr 2023 15:24
Last Modified:	08 Apr 2025 06:51

Cite in APA 7:	Rayapati, V. N., & Kaminska, B. (1996). Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip. IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part B, Advanced Packaging, 19(3), 605-614. https://doi.org/10.1109/96.533903
APA 7 (HTML)ASCII CitationAtomBibTeXDOIsDublin CoreEndNote (.ENW)MARC (ISO 2709/UTF-8) (.MRC)MARC (UTF-8) (.MRK8)MARC XMLMPEG-21 DIDLMultiline CSVOAI-ORE Resource Map (Atom Format)OPENAIREOpenURL ContextObjectOpenURL ContextObject in SpanRDF+N-TriplesRDF+N3RDF+XMLReferReference Manager (.RIS)Simple Metadata

Statistics

Repository Staff Only