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On the design of at-speed testable VLSI circuits

M. Soufi, Yvon Savaria and Bozena Kaminska

Paper (1995)

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Additional Information: Nom historique du département: Département de génie électrique et de génie informatique
Department: Department of Electrical Engineering
Department of Computer Engineering and Software Engineering
PolyPublie URL: https://publications.polymtl.ca/31713/
Conference Title: 13th IEEE VLSI Test Symposium
Conference Location: Princeton, NJ, USA
Conference Date(s): 1995-04-30 - 1995-05-03
Publisher: IEEE
DOI: 10.1109/vtest.1995.512651
Official URL: https://doi.org/10.1109/vtest.1995.512651
Date Deposited: 18 Apr 2023 15:25
Last Modified: 05 Apr 2024 11:21
Cite in APA 7: Soufi, M., Savaria, Y., & Kaminska, B. (1995, April). On the design of at-speed testable VLSI circuits [Paper]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. https://doi.org/10.1109/vtest.1995.512651



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