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Testability Analysis and Test-Point Insertion in Rtl Vhdl Specifications for Scan-Based Bist

S. Boubezari, E. Cerny, Bozena Kaminska and B. Nadeau-Dostie

Article (1999)

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Additional Information: Nom historique du département: Département de génie électrique et de génie informatique
Department: Department of Electrical Engineering
Department of Computer Engineering and Software Engineering
PolyPublie URL: https://publications.polymtl.ca/29106/
Journal Title: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (vol. 18, no. 9)
Publisher: IEEE
DOI: 10.1109/43.784124
Official URL: https://doi.org/10.1109/43.784124
Date Deposited: 18 Apr 2023 15:22
Last Modified: 05 Apr 2024 11:17
Cite in APA 7: Boubezari, S., Cerny, E., Kaminska, B., & Nadeau-Dostie, B. (1999). Testability Analysis and Test-Point Insertion in Rtl Vhdl Specifications for Scan-Based Bist. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(9), 1327-1340. https://doi.org/10.1109/43.784124

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