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Aubin, F., Slamani, M., Kaminska, B., & Robert, J.-M. (1991, October). Biolink: A New Myoelectric Pointing Device For interactive Computer Systems: Evaluation Of The Human Performance And Integrated Realization [Paper]. Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Orlando, FL. External link
Boyogueno Bendé, A., Kaminska, B., & Slamani, M. (2000, May). A preamplifier IC design for photonic links [Paper]. IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century (ISCAS 2000 Geneva), Geneva, Switzerland. External link
Boubezari, S., Cerny, E., Kaminska, B., & Nadeau-Dostie, B. (1999). Testability Analysis and Test-Point Insertion in Rtl Vhdl Specifications for Scan-Based Bist. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(9), 1327-1340. External link
Boyogueno Bendé, A., & Kaminska, B. (1998, September). Broad-band low-noise preamplifier design with GaAs MESFETs for optical communication systems [Paper]. URSI International Symposium on Signal, Systems, and Electronics, Pisa, Italy. External link
Boubezari, S., & Kaminska, B. (1996). New reconfigurable test vector generator for built-in self-test applications. Journal of Electronic Testing: Theory and Applications (JETTA), 8(2), 153-164. External link
Belhaouane, A., Savaria, Y., & Kaminska, B. (1996, January). Reconstruction method for data acquisition systems with randomly distributed jitter [Paper]. 2nd IEEE International Mixed Signal Testing Workshop. Unavailable
Belhaouane, A., Savaria, Y., Kaminska, B., & Massicotte, D. (1996). Reconstruction method for jitter tolerant data acquisition system. Journal of Electronic Testing: Theory and Applications, 9(1-2), 177-185. External link
Ben-Hamida, N., Ayari, B., & Kaminska, B. (1996, October). Testing of embedded A/D converters in mixed-signal circuit [Paper]. 1996 International Conference on Computer Design, ICCD'96, Austin, TX, USA. External link
Bechir, A., & Kaminska, B. (1995, April). BDD_FTEST: fast, backtrack-free test generator based on binary decision diagram representation [Paper]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. Unavailable
Bechir, A., & Kaminska, B. (1995). CYCLOGEN: Automatic, functional-level test generator based on the cyclomatic complexity measure and on the ROBDD representation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42(7), 446-452. External link
Boubezari, S., & Kaminska, B. (1995). Deterministic built-in self-test generator based on cellular automata structures. IEEE Transactions on Computers, 44(6), 805-816. External link
Boubezari, S., & Kaminska, B. (1995, April). Mixed deterministic and pseudorandom test vector generator based on cellular automata structures [Paper]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. External link
BenHamida, H., & Kaminska, B. (1994, May). High level synthesis with testability constraints [Paper]. IEEE International Symposium on Circuits and Systems - ISCAS '94, London, UK. External link
BenHamida, N., Kaminska, B., & Savaria, Y. (1994, May). Pseudo-random vector compaction for sequential testability [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England. External link
Ehsanian, M., Kaminska, B., & Arabi, K. (1998). New on-Chip Digital Bist for Analog-to-Digital Converters. Microelectronics and reliability, 38(3), 409-420. External link
Ehsanian, M., Hamida, N. B., & Kaminska, B. (1997, June). Novel A/D converter for high-resolution and high-speed applications [Paper]. 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97, Hong Kong, Hong Kong. External link
Ehsanian, M., & Kaminska, B. (1996). BiCMOS wideband operational amplifier with 900 MHz gain-bandwidth and 90 dB DC gain. Analog Integrated Circuits and Signal Processing, 11(1), 63-71. External link
Ehsanian, M., Kaminska, B., & Arabi, K. (1996, April). New digital test approach for analog-to-digital converter testing [Paper]. 1996 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Fares, M., & Kaminska, B. (1994, May). Test strategy selection for multi-chip systems [Paper]. 1994 3rd International Conference on the Economics of Design, Test, and Manufacturing, Austin, TX, USA. External link
Fares, M., & Kaminska, B. (1995). FPAD: a fuzzy nonlinear programming approach to analog circuit design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14(7), 785-793. External link
Fares, M., & Kaminska, B. (1994). Fuzzy optimization models for analog test decisions. Journal of Electronic Testing: Theory and Applications (JETTA), 5(2-3), 299-305. External link
Fares, M., & Kaminska, B. (1994). Exploring test space with fuzzy decision making. IEEE Design & Test of Computers, 11(3), 17-27. External link
Gagnon, M., & Kaminska, B. (1997, November). Optical communication channel test using BIST approaches [Paper]. 1997 IEEE International Test Conference, Washington, DC, USA. External link
Gadiri, A., Savaria, Y., & Kaminska, B. (1995, September). Optimized CMOS compatible photoreceiver [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montréal, QC, Canada. External link
Hamida, N. B., Saab, K., Marche, D., Kaminska, B., & Quesnel, G. (1996, October). LIMSoft: Automated tool for design and test integration of analog circuits [Paper]. 1996 IEEE International Test Conference, Washington, DC, USA. External link
Hamida, N. B., & Kaminska, B. (1994, January). Multiple fault testing in analog circuits [Paper]. 7th International Conference on VLSI Design, Calcutta, India. External link
Jamoussi, M., Amellal, S., & Kaminska, B. (1998, December). High-level testability evaluation of TASS synthesized systems [Paper]. 10th International Conference on Microelectronics (ICM 1998), Monastir, Tunisia. External link
Jamoussi, M., & Kaminska, B. (1994, January). Data path testability evaluation via functional testability measures [Paper]. 7th International Conference on VLSI Design, Calcutta, India. External link
Jamoussi, M., & Kaminska, B. (1994, February). M-testability: An approach for data-path testability evaluation [Paper]. European Design and Test Conference, Paris, Fr. External link
Jamoussi, M., Kaminska, B., & Mukhedkar, D. (1992, January). A New variable testability measure: A concept for data-flow testability evaluation [Paper]. 5th International Conference on VLSI Design (ICVD 1992), Bangalore, India. External link
Kaminska, B., & Courtois, B. (1996). Guest editors introduction - mixed analog and digital-systems. IEEE Design & Test of Computers, 13(2), 8-9. External link
Kaminska, B. (1996). IEEE mixed-signal testing workshop. IEEE Design & Test of Computers, 13(3), 114-114. Unavailable
Khaled, S., Kaminska, B., Courtois, B., & Lubaszewski, M. (1995, April). Frequency-based BIST for analog circuit testing [Paper]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Lejmi, S., Kaminska, B., & Ayari, B. (1995, April). Retiming for BIST-sequential circuits [Paper]. 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, Seattle, WA, USA. External link
Lejmi, S., Kaminska, B., & Ayari, B. (1995, April). Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits [Paper]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Lejmi, S., Kaminska, B., & Ayari, B. (1995, October). Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits [Paper]. 1995 26th International Test Conference, Washington, DC, USA. External link
Lejmi, S., Kaminska, B., & Wagneur, E. (1994, October). Retiming for the global optimization of synchronous sequential circuits [Paper]. IEEE International Conference on Computer Design: VLSI in Computers and Processors, Cambridge, MA, USA. External link
Mheir-El-Saadi, F., & Kaminska, B. (1994). Automatic hierarchical delay analysis tool. Journal of Computer Science and Technology, 9(4), 349-364. External link
Ondghiri, H., Kaminska, B., & Rajski, J. (1997, May). A hardware/software partitioning technique with hierarchical design space exploration [Paper]. CICC 97 - Custom Integrated Circuits Conference, Santa Clara, CA, USA. External link
Oudghiri, H., & Kaminska, B. (1991). Global weighted scheduling and allocation algorithms. (Technical Report n° EPM-RT-91-01). Restricted access
Oudghiri, H., & Kaminska, B. (1991). Synthèse de haut niveau : ordonnancement et allocation. (Technical Report n° EPM-RT-91-02). Restricted access
Rayapati, V. N., & Kaminska, B. (1997). Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation. Microelectronics and reliability, 37(5), 785-794. External link
Rayapati, V. N., & Kaminska, B. (1996). Interconnect propagation delay modeling and validation for the 16-MB CMOS SRAM chip. IEEE Transactions on Components, Packaging, and Manufacturing Technology. Part B, Advanced Packaging, 19(3), 605-614. External link
Rzeszut, J., Kaminska, B., & Savaria, Y. (1995, November). New method for testing mixed analog and digital circuits [Paper]. 4th Asian Test Symposium, Bangalore, India. External link
Rayapati, V. N., & Kaminska, B. (1994). A dynamic reconfiguration scheme for mega bit static random access memories. Microelectronics and reliability, 34(1), 107-114. External link
Rayapati, V. N., & Kaminska, B. (1994, August). Mega bit BiCMOS SRAM chip package modelling and performance analysis [Paper]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, Cal, USA. External link
Rayapati, V. N., & Kaminska, B. (1994, August). Mega bit CMOS SRAM chip failure analysis using external electrical testing and internal contactless laser beam testing [Paper]. IEEE International Workshop on Memory Technology, Design, and Testing, San Jose, Cal, USA. External link
Rayapati, V. N., & Kaminska, B. (1993, August). Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs [Paper]. IEEE International Workshop on Memory Testing (MT 1993), San Jose, CA, United states. External link
Sylla, I. T., Slamani, M., Kaminska, B., Hossein, F. M., & Vincent, P. (1998, April). Impedance mismatch and lumped capacitance effects in high frequency testing [Paper]. 16th IEEE VLSI Test Symposium, Monterey, CA, USA. External link
Sokolowska, E., Fortin, G., Belabbes, N., Gagnon, M., & Kaminska, B. (1998, September). Scalable pseudo-optical switching system for multi-protocol environment [Paper]. IEEE International Conference on Electronics, Circuits, and Systems, Lisboa, Portugal. External link
Sokolowska, E., Fortin, G., Belabbes, N., Gagnon, M., Roy, C., & Kaminska, B. (1997, October). Bidirectional analog 8 & times; 8 switch matrix with large input signal and over 1 GHz bandwidth [Paper]. 1997 19th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, Anaheim, CA, USA. External link
Sokolowska, E., Belabbes, N., & Kaminska, B. (1997, June). Integrated analog switch matrix with large input signal and 46dB isolation at 1GHz [Paper]. 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97, Hong Kong, Hong Kong. External link
Sylla, I.-T., Slamani, M., Kaminska, B., & Ghannouchi, F. M. (1997). Joint design and test consideration in high frequency circuits. Microwave and Optical Technology Letters, 16(3), 132-138. External link
Soufi, M., Rochon, S., Savaria, Y., & Kaminska, B. (1996, April). Design and performance of CMOS TSPC cells for high speed pseudo random testing [Paper]. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Slamani, M., & Kaminska, B. (1996). Fault observability analysis of analog circuits in frequency-domain. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 43(2), 134-139. External link
Sokolowska, E., Belabbes, N. E., & Kaminska, B. (1996, April). Integrated analog switch matrix with large input signal and 46dB isolation at 1 GHz [Paper]. 1996 International IFIP-IEEE Conference on Broadband Communications, Montréal, Québec. External link
Saab, K., Marche, D., Hamida, N. B., & Kaminska, B. (1996). LIMSoft : automated tool for sensitivity analysis and test vector generation : Mixed signal & analogue IC test technology. IEE Proceedings. Circuits, Devices and Systems, 143(6), 386-392. External link
Slamani, M., & Kaminska, B. (1995). Multifrequency analysis of faults in analog circuits. IEEE Design & Test of Computers, 12(2), 70-80. External link
Soufi, M., Savaria, Y., & Kaminska, B. (1995, April). On the design of at-speed testable VLSI circuits [Paper]. 13th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Soufi, M., Savaria, Y., & Kaminska, B. (1995, April). On Using partial reset for pseudo-random testing [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA. External link
Soufi, M., Savaria, Y., Darlay, F., & Kaminska, B. (1995). Producing reliable initialization and test of sequential circuits with pseudorandom vectors. IEEE Transactions on Computers, 44(10), 1251-1256. External link
Sokolowska, E., & Kaminska, B. (1994, October). Application of optoelectronic techniques to high speed testing [Paper]. 1994 IEEE International Test Conference, Washington, DC, USA. External link
Slamani, M., Kaminska, B., & Quesnel, G. (1994, October). Integrated approach for analog circuit testing with a minimum number of detected parameters [Paper]. 1994 IEEE International Test Conference, Washington, DC, USA. External link
Slamani, M., & Kaminska, B. (1994, April). Multifrequency testability analysis for analog circuits [Paper]. 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, USA. External link
Soufi, M., Savaria, Y., Kaminska, B., & Darlay, F. (1994). Producing reliable initialization and test of sequential circuits with pseudo-random vectors. (Technical Report n° EPM-RT-94-23). Restricted access
Slamani, M., & Kaminska, B. (1993, November). T-BIST: A built-in self-test for analog circuits based on parameter translation [Paper]. 2nd IEEE Asian Test Symposium (ATS 1993), Beijing, China. External link
