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Soufi, M. (1997). Caractérisation et amélioration de la testabilité séquentielle pseudo-aléatoire des circuits VLSI [Ph.D. thesis, École Polytechnique de Montréal]. Available
Soufi, M., Rochon, S., Savaria, Y., & Kaminska, B. (1996, April). Design and performance of CMOS TSPC cells for high speed pseudo random testing [Paper]. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA. External link
Soufi, M., Savaria, Y., Kaminska, B., & Darlay, F. (1994). Producing reliable initialization and test of sequential circuits with pseudo-random vectors. (Technical Report n° EPM-RT-94-23). Restricted access
