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Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers

Ahmed Abuelnasr, Mostafa Amer, Mohamed Ali, Ahmad Hassan, Benoît Gosselin, Ahmed Ragab Anwar Ragab and Yvon Savaria

Article (2023)

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Abstract

The Design of efficient, safe, and reliable circuits is a prime objective in high-voltage (HV) electronic systems, such as switched-mode power amplifiers (PAs). One of the main causes of efficiency degradation and reliability problems, in these amplifiers, is the shoot-through current from the HV power supply to the ground. To eliminate such current, a dead time generator (DTG) is used to modify the signals propagating through the high-side and low-side gate drivers by adding a fixed dead time between them. However, any delay mismatch between these gate drivers can reduce the dead time to the point that it becomes negative. In this paper, an HV-DTG architecture is introduced. The architecture mitigates the effects of delay mismatch variations in gate drivers, which can result from parameters mismatch, fabrication process variations, and temperature variations. An HV switched-mode class-D power amplifier is used to illustrate the performance of the DTG. The amplifier is implemented in a low-cost 0.35 μm HV CMOS process. The total area of the PA is 0.5 mm² , where the DTG covers an area of 0.066 mm² . A measured system’s efficiency of 95.14% is achieved with the shortest dead time of 10.8 ns, which is 1.38x smaller than the generated dead time in comparable state-of-the-art HV dead time generators.

Uncontrolled Keywords

Dead time generator; power amplifiers; switched-mode power amplifiers; class-D amplifier; highefficiency circuits; fabrication process & temperature variations; shoot-through current

Subjects: 2500 Electrical and electronic engineering > 2500 Electrical and electronic engineering
Department: Department of Electrical Engineering
Funders: CRSNG/NSERC, MITACS
PolyPublie URL: https://publications.polymtl.ca/52205/
Journal Title: IEEE Transactions on Circuits and Systems I: Regular Papers (vol. 70, no. 4)
Publisher: IEEE
DOI: 10.1109/tcsi.2022.3232074
Official URL: https://doi.org/10.1109/tcsi.2022.3232074
Date Deposited: 18 Apr 2023 14:58
Last Modified: 10 Apr 2024 00:43
Cite in APA 7: Abuelnasr, A., Amer, M., Ali, M., Hassan, A., Gosselin, B., Ragab, A. R. A., & Savaria, Y. (2023). Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(4), 1555-1565. https://doi.org/10.1109/tcsi.2022.3232074

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