H. T. Vinh, D. Audet and Yvon Savaria
Paper (1993)
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| Department: | Department of Electrical Engineering |
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| PolyPublie URL: | https://publications.polymtl.ca/43906/ |
| Conference Title: | Canadian Conference on Electrical and Computer Engineering (CCECE 1993) |
| Conference Location: | Vancouver, BC, Canada |
| Conference Date(s): | 1993-09-14 - 1993-09-17 |
| Publisher: | IEEE |
| DOI: | 10.1109/ccece.1993.332331 |
| Official URL: | https://doi.org/10.1109/ccece.1993.332331 |
| Date Deposited: | 18 Apr 2023 15:26 |
| Last Modified: | 05 May 2023 15:48 |
| Cite in APA 7: | Vinh, H. T., Audet, D., & Savaria, Y. (1993, September). Performance models for optimizing a hierarchical-bus multiprocessor architecture [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 1993), Vancouver, BC, Canada. https://doi.org/10.1109/ccece.1993.332331 |
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