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Items where Author is "Audet, D."

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Number of items: 15.

A

Audet, D., Masson, S., & Savaria, Y. (1998, November). Reducing fault sensitivity of microprocessor-based systems by modifying workload structure [Paper]. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 1998), Austin, TX. External link

Audet, D., Gagnon, N., & Savaria, Y. (1996, January). Implementing fault injection and tolerance mechanisms in multiprocessor systems [Paper]. IEEE Workshop on Defect and Fault Tolerance in VLSI (DFT 1996), Boston. External link

Audet, D., Gagnon, F., & Savaria, Y. (1996, January). Quantitative comparisons of TMR implementations in a multiprocessor system [Paper]. 3rd IEEE On-Line Testing Workshop, Biarritz. Unavailable

Audet, D., & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the host interface. (Technical Report). Unavailable

Audet, D., & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the routers, from a functional to a detailed implementation description. (Technical Report). Unavailable

Audet, D., Savaria, Y., & Arel, N. (1995). Effective ultra large scale integration (ULSI) architecture techniques: FATMOS, a fault-tolerant multiprocessor operating system. (Technical Report). Unavailable

Audet, D., & Savaria, Y. (1995). High-speed interconnections using true single-phase clocking. Journal of Microelectronic Systems Integration, 3(4), 247-257. Unavailable

Audet, D., & Savaria, Y. High-speed interconnections using true single-phase clocking [Paper]. 7th IEEE Annual International Conference on Wafer Scale Integration, San Francisco, Ca, USA. External link

Audet, D., & Savaria, Y. (1994). Architectural approach for increasing clock frequency and communication speed in monolithic WSI systems. IEEE Transactions on Components Packaging and Manufacturing Technology. Part B, Advanced Packaging, 17(3), 362-368. External link

Audet, D., Savaria, Y., & Arel, N. (1994, January). Architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems [Paper]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, California. External link

Audet, D., Savaria, Y., & Arel, N. (1994). Pipelining communications in large VLSI/ULSI systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1), 1-10. External link

K

Kermouche, R., Audet, D., & Savaria, Y. (1995). On the optimization of integrated hierarchical bus architectures to achieve efficient fault-tolerance. Journal of Microelectronic Systems Integration, 3(1), 47-63. Unavailable

Kermouche, R., Savaria, Y., & Audet, D. (1994, January). Harvest model of an integrated hierarchical-bus architecture [Paper]. 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA. External link

T

Thériault, L., Audet, D., & Savaria, Y. (2001, May). Performance estimators for hardware/software co-design [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie. External link

V

Vinh, H. T., Audet, D., & Savaria, Y. (1993, September). Performance models for optimizing a hierarchical-bus multiprocessor architecture [Paper]. Canadian Conference on Electrical and Computer Engineering (CCECE 1993), Vancouver, BC, Canada. External link

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