Meng Lu, Yvon Savaria, Bing Qiu and Jacques Taillefer
Paper (2003)
An external link is available for this itemDepartment: | Department of Electrical Engineering |
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PolyPublie URL: | https://publications.polymtl.ca/35588/ |
Conference Title: | 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003) |
Conference Location: | Boston, MA, United states |
Conference Date(s): | 2003-11-03 - 2003-11-05 |
Publisher: | IEEE |
DOI: | 10.1109/dftvs.2003.1250091 |
Official URL: | https://doi.org/10.1109/dftvs.2003.1250091 |
Date Deposited: | 18 Apr 2023 15:20 |
Last Modified: | 25 Sep 2024 16:19 |
Cite in APA 7: | Lu, M., Savaria, Y., Qiu, B., & Taillefer, J. (2003, November). IEEE 1149.1 based defect and fault tolerant scan chain for wafer scale integration [Paper]. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states. https://doi.org/10.1109/dftvs.2003.1250091 |
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