A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management

Michel Gemieux, Meng Li, Yvon Savaria, Jean Pierre David and Guchuan Zhu

Article (2018)

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Department:	Department of Electrical Engineering
Research Center:	GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL:	https://publications.polymtl.ca/41406/
Journal Title:	IEEE Access (vol. 6)
Publisher:	IEEE
DOI:	10.1109/access.2018.2876597
Official URL:	https://doi.org/10.1109/access.2018.2876597
Date Deposited:	18 Apr 2023 15:03
Last Modified:	08 Apr 2025 07:05

Cite in APA 7:	Gemieux, M., Li, M., Savaria, Y., David, J. P., & Zhu, G. (2018). A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access, 6, 62826-62839. https://doi.org/10.1109/access.2018.2876597
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