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Jean Pierre DavidDepartment of Electrical Engineering
Profile in the Directory of Experts of Polytechnique Montréal
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Askarihemmat, M., Wagner, S., Bilaniuk, O., Hariri, Y., Savaria, Y., & David, J. P. (2023, January). BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU [Paper]. 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023), Tokyo, Japan. External link
AskariHemmat, M.H., Dupuis, T., Fournier, Y., El Zarif, N., Cavalcante, M., Perotti, M., Gurkaynak, F., Benini, L., Leduc-Primeau, F., Savaria, Y., & David, J. P. Quark: an integer RISC-V vector processor for sub-byte quantized DNN inference [Paper]. 2023 IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, CA, USA (5 pages). External link
Audet, Y., Bendali, A., & David, J. P. (2021). A CMOS Photodetector for or Direct Color Imaging. IEEE Transactions on Electron Devices, 68(3), 1107-1114. External link
AskariHemmat, M.H., Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (2021, May). RISC-V barrel processor for deep neural network acceleration [Paper]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). External link
Abdelsalam, A. M., Elsheikh, A., Chidambaram, S., David, J. P., & Langlois, J. M. P. (2020). POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. Journal of Signal Processing Systems, 92(1), 95-107. External link
Askarihemmat, M.H., Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (2020, May). RISC-V Barrel Processor for Accelerator Control [Paper]. 28th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2020), Fayetteville, AR (1 page). External link
Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (2019, October). POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests [Paper]. 13th Conference on Design and Architectures for Signal and Image Processing (DASIP 2019), Montréal, Qc, Canada. External link
AskariHemmat, M.H., Honari, S., Rouhier, L., Perone, C. S., Cohen-Adad, J., Savaria, Y., & David, J. P. (2019, October). U-net fixed-point quantization for medical image segmentation [Paper]. 1st International Workshop on Hardware Aware Learning for Medical Imaging and Computer Assisted Intervention (HAL-MICCAI 2019), Shenzhen, China. External link
Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (2018, October). POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA [Paper]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal. External link
Allard, M., Grogan, P., Savaria, Y., & David, J. P. (2012, May). Two-level configuration for FPGA: A new design methodology based on a computing fabric [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. External link
Allard, M., Grogan, P., & David, J. P. (2009, December). A scalable architecture for multivariate polynomial evaluation on FPGA [Paper]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2009), Cancun, Mexico. External link
Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (2021). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models. In The Lognormality Principle and its Applications in e-Security, e-Learning and e-Health (Vol. 88, pp. 309-325). External link
Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (2019, May). Bit-slicing FPGA accelerator for quantized neural networks [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). External link
Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (2019, June). Combining Interval Arithmetic with the Branch and Bound Algorithm for Delta-lognormal Parameter Extraction [Paper]. International Conference of the International Graphonomics Society, Cancun, Mexico (5 pages). Unavailable
Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (2018, May). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models [Paper]. International Conference on Pattern Recognition and Artificial Intelligence (ICPRAI 2018), Montréal, Québec. Unavailable
Blanchette, H. F., Ould-Bachir, T., & David, J. P. (2012). A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Transactions on Industrial Electronics, 59(12), 4555-4567. External link
Bergeron, E., Perron, L. D., Feeley, M., & David, J. P. (2011). Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. ACM Transactions on Reconfigurable Technology and Systems, 4(2), 1-27. External link
Bafumba-Lokilo, D., Savaria, Y., & David, J. P. (2009, October). Generic array-based MPSoC architecture [Paper]. 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada. External link
Bafumba-Lokilo, D., Savaria, Y., & David, J. P. (2008, June). Generic crossbar network on chip for FPGA MPSoCs [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link
Bergeron, E., Feeley, M., & David, J. P. (2008, March). Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs [Paper]. 17th International Conference on Compiler Construction (CC 2008), Budapest, Hungary. External link
Bergeron, E., Feeley, M., Daigneault, M.-A., & David, J. P. (2008, June). Using dynamic reconfiguration to implement high-resolution programmable Delays on an FPGA [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec. External link
Bergeron, E., Feeley, M., & David, J. P. (2007, August). Toward on-chip JIT synthesis on Xilinx VirtexII-Pro FPGAs [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. External link
Brassard, O., Rousseau, F., David, J. P., Kastle, M., & Aboulhamid, E. M. (2006, June). Automatic generation of embedded systems with .NET framework based tools [Paper]. IEEE North-East Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Québec, Canada. External link
Bergeron, E., Saint-Mleux, X., Feeley, M., & David, J. P. (2005, June). High level synthesis for data-driven applications [Paper]. 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), Montréal, Québec. External link
Chiu, T.-Y., Le Ny, J., & David, J. P. (2024). Temporal Logic Explanations for Dynamic Decision Systems Using Anchors and Monte Carlo Tree Search (Abstract Reprint). Proceedings of the AAAI Conference on Artificial Intelligence, 38(20), 22694-22694. External link
Chiu, T.-Y., Le Ny, J., & David, J. P. (2023). Temporal logic explanations for dynamic decision systems using anchors and Monte Carlo Tree Search. Artificial Intelligence, 318, 21 pages. External link
Chidambaram, S., Langlois, J. M. P., & David, J. P. (2020, March). PoET-BiN : Power Efficient Tiny Binary Neurons [Paper]. 3rd Conference on Machine Learning and Systems (MLSys 2020), Austin, Texas (12 pages). Unavailable
Chidambaram, S., Riviello, A., Langlois, J. M. P., & David, J. P. (2018, October). Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors [Paper]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal. External link
Courbariaux, M., Bengio, Y., & David, J. P. (2015, December). BinaryConnect: Training deep neural networks with binary weights during propagations [Paper]. 28th Conference on Advances in Neural Information Processing Systems (NIPS 2015), Montréal, Québec. Unavailable
Courbariaux, M., Bengio, Y., & David, J. P. (2015, May). Training deep neural networks with low precision multiplications [Paper]. International Conference on Learning Representations (ICLR 2015), San Diego, Calif. (10 pages). External link
Dufour, J., Savaria, Y., & David, J. P. Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries [Paper]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). External link
Dupuis, T., Fournier, Y., AskariHemmat, M.H., Zarif, N. E., Leduc-Primeau, F., David, J. P., & Savaria, Y. (2023, June). Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference [Paper]. 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). External link
Daigneault, M.-A., & David, J. P. (2018). Automated synthesis of streaming transfer level hardware designs. ACM Transactions on Reconfigurable Technology and Systems, 11(2), 1-22. External link
David, J. P. (2017). Low latency and division free Gauss-Jordan solver in floating point arithmetic. Journal of Parallel and Distributed Computing, 106, 185-193. External link
David, J. P. (2016). File presence detection and monitoring. (Patent no. US9264434). External link
Daigneault, M.-A., & David, J. P. (2015, May). Intermediate-level synthesis of a Gauss-Jordan elimination linear solver [Paper]. 29th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015), Hyderabad, India. External link
David, J. P. (2015, December). Low latency solver for linear equation systems in floating point arithmetic [Paper]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Mexico City, Mexico (7 pages). External link
Daigneault, M.-A., & David, J. P. (2014). Fast description and synthesis of control-dominant circuits. Computers and Electrical Engineering, 40(4), 1199-1214. External link
Daigneault, M.-A., & David, J. P. (2013, February). Hardware description and synthesis of control-intensive reconfigurable dataflow architectures [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, Calif.. External link
Daigneault, M.-A., & David, J. P. (2013, April). High-level description and synthesis of floating-point accumulators on FPGA [Paper]. 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA, United states. External link
David, J. P. (2013, December). Max-hashing fragments for large data sets detection [Paper]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2013), Cancun, Mexico (6 pages). External link
Daigneault, M.-A., & David, J. P. (2012, August). Raising the abstraction level of HDL for control-dominant applications [Paper]. 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway. External link
Daigneault, M. A., & David, J. P. Synchronized-Transfer-Level Design Methodology Applied to Hardware Matrix Multiplication [Paper]. International Conference on Reconfigurable Computing and Fpgas (Reconfig 2012), Cancun, Mexico (7 pages). External link
Daigneault, M.-A., & David, J. P. (2011). A high-resolution time-to-digital converter on FPGA using dynamic reconfiguration. IEEE Transactions on Instrumentation and Measurement, 60(6), 2070-2079. External link
Daigneault, M., & David, J. P. (2010, June). A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA [Paper]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. External link
Daigneault, M.-A., & David, J. P. (2010, February). Towards 5ps resolution TDC on a dynamically reconfigurable FPGA [Abstract]. 8th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California. External link
Daigneault, M.-A., Langlois, J. M. P., & David, J. P. (2008, October). Application Specific Instruction set processor specialized for block motion estimation [Paper]. IEEE International Conference on Computer Design (ICCD 2008), Lake Tahoe, CA. External link
David, J. P., Kalach, K., & Tittley, N. (2007). Hardware Complexity of Modular Multiplication and Exponentiation. IEEE Transactions on Computers, 56(10), 1308-1319. External link
David, J. P., & Bergeron, E. (2004, September). An intermediate level HDL for system level design [Paper]. 7th Forum on Specification and Design Languages (FDL 2004), Lille, France. Unavailable
David, J. P., & Bergeron, E. (2004, July). A step towards intelligent translation from high-level design to RTL [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2004), Banff, Canada. External link
David, J. P. (2002). Architecture synchronisée par les données pour système reconfigurable [Ph.D. Thesis, Université catholique de Louvain]. Unavailable
David, J. P., & Legat, J.-D. (2002, December). System C: une perspective pour la conception simultanée logiciel/matériel de systèmes utilisant des ressources synchronisées par les données [Paper]. Journées Francophones sur l'Adéquation Algorithme Architecture (JFAAA 2002), Monastir, Tunisie. Unavailable
David, J. P., Postiau, T., Fisette, P., & Legat, J.-D. (2001, April). Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications [Paper]. 15th International Parallel & Distributed Processing Symposium (IPDPS 2001), San Francisco, CA. Unavailable
David, J. P., & Legat, J.-D. (1998, June). A data-flow oriented co-design for reconfigurable systems [Paper]. 9th International Workshop on Rapid System Prototyping, Leuven, Belgium. External link
David, J. P., & Legat, J.-D. (1997, December). A 400Kgates, 8Mbytes SRAM multi-FPGA PCI system [Paper]. International Workshop on Logic and Architecture Synthesis (IWLS 1997), Grenoble, France. Unavailable
El Zarif, N., Hemmat, M. A., Dupuis, T., David, J. P., & Savaria, Y. (2024). Polara-Keras2c: Supporting Vectorized AI Models on RISC-V Edge Devices. IEEE Access, 12, 171836-171852. External link
Ehmer, J., Savaria, Y., Granado, B., David, J. P., & Denoulet, J. (2024). Network Attack Classification with a Shallow Neural Network for Internet and Internet of Things (IoT) Traffic. Electronics, 13(16), 3318-3318. External link
Elbediwy, M., Pontikakis, B., Ghaffari, A., David, J. P., & Savaria, Y. (2024). DR-PIFO: a dynamic ranking packet scheduler using a push-in-first-out queue. IEEE Transactions on Network and Service Management, 21(1), 355-371. External link
Elbediwy, M., Pontikakis, B., David, J. P., & Savaria, Y. (2023). A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access, 11, 61422-61436. Available
Ebrahimi, A., Pullu, V. N., Langlois, J. M. P., & David, J. P. Iterative pruning algorithm for efficient look-up table implementation of binary neural networks [Paper]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages). External link
Ehmer, J., Granado, B., Denoulet, J., Savaria, Y., & David, J. P. (2022, June). Low complexity shallow neural network with improved false negative rate for cyber intrusion detection systems [Paper]. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada. External link
Gemieux, M., Li, M., Savaria, Y., David, J. P., & Zhu, G. (2018). A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access, 6, 62826-62839. External link
Gémieux, M., Savaria, Y., David, J. P., & Zhu, G. (2017, May). A cache-coherent heterogeneous architecture for low latency real time applications [Paper]. 20th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2017), Toronto, ON, Canada. External link
Hajizadeh, F., Ould-Bachir, T., & David, J. P. (2024). CuFP: An HLS Library for Customized Floating-Point Operators. Electronics, 13(14), 2838 (22 pages). External link
Humblet, E., Dupuis, T., Fournier, Y., AskariHemmat, M. H., Leduc-Primeau, F., David, J. P., & Savaria, Y. (2024, August). MSPARQ: A RISC-V Vector Processor Array Optimized for Low-Resolution Neural Networks [Paper]. IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS 2024), Springfield, MA, USA. External link
Hajizadeh, F., Alavoine, L., Ould-Bachir, T., Sirois, F., & David, J. P. (2023, August). FPGA-based FDNE models for the accurate real-time simulation of power systems in aircraft [Paper]. 12th International Conference on Renewable Energy Research and Application, Oshawa, ON, Canada (5 pages). External link
Hamine, M., Audet, Y., & David, J. P. (2007, August). A real time image reconstruction algorithm for an integrated fingerprint sensor [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec. External link
Kaced, K., Genevey, S., Savaria, Y., & David, J. P. (2024, June). A Flexible Thermal/Solar Energy Harvesting System with Hysteretic Control and Maximum Power Point Tracking Regulation for IoT Devices [Paper]. 22nd IEEE Interregional NEWCAS Conference (NEWCAS 2024), Piscataway, NJ, USA. External link
Khanzadi, H., Savaria, Y., & David, J. P. (2017, June). A data driven CGRA Overlay Architecture with embedded processors [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France. External link
Khanzadi, H., Savaria, Y., & David, J. P. (2015, June). Mapping applications on two-level configurable hardware [Paper]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec (8 pages). External link
Kalach, K., & David, J. P. (2005, August). Hardware implementation of large number multiplication by FFT with modular arithmetic [Paper]. 3rd International IEEE-NEWCAS Conference (NEWCAS 2005), Québec, Québec. External link
Larbanet, A., Lerebours, J., & David, J. P. (2015, August). Detecting very large sets of referenced files at 40/100 GbE, especially MP4 files [Paper]. 15th Annual DFRWS Conference (DFRWS USA 2015), Philadelphia, PA, USA. Published in Digital Investigation, 14(suppl. 1). Available
Lapalme, J., Aboulhamed, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (2004, June). Esys.net: A New Solution for Embedded Systems Modeling and Simulation [Paper]. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C.. Published in ACM Sigplan Notices, 39(7). External link
Lapalme, J., Aboulhamid, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (2004, February). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France. External link
Legat, J.-D., & David, J. P. (1998, May). Design of a multi-FPGA system for rapid prototyping experimentation [Paper]. 2nd European Workshop on Microelectronics Education, Noordwijkerhout, The Netherlands. External link
Legat, J.-D., & David, J. P. (1998, November). A FPGA-based implementation of adaptive sound filtering [Paper]. 9th International Conference on Circuits, Systems, and Signal Processing (CSSP 1998), Mierlo, The Netherlands. Unavailable
Legat, J.-D., & David, J. P. (1998, March). A multi-FPGA based coprocessor for digital signal processing [Paper]. IEEE Benelux Signal Processing Symposium (SPS 1998), Leuven, Belgium. Unavailable
Legat, J.-D., & David, J. P. (1998, April). Programmable architectures for subband coding: FPGA-based systems versus dedicated VLSI chip [Paper]. 2nd IMACS Multiconference on Computational Engineering in Systems Applications (CESA 1998), Nabeul-Hammamet, Tunisia. Unavailable
Montaño, F., Ould-Bachir, T., & David, J. P. (2020). A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators. Electronics, 9(11), 21 pages. External link
Montano, F., Ould-Bachir, T., Mahseredjian, J., & David, J. P. (2019, May). A Low-Latency Reconfigurable Multistage Interconnection Network [Paper]. IEEE Canadian Conference of Electrical and Computer Engineering (CCECE 2019), Edmonton, AB, Canada (4 pages). External link
Montano, F., Ould-Bachir, T., & David, J. P. (2018). An evaluation of a high-level synthesis approach to the FPGA-based submicrosecond real-time simulation of power converters. IEEE Transactions on Industrial Electronics, 65(1), 636-644. External link
Ould-Bachir, T., Dufour, C., Bélanger, J., Mahseredjian, J., & David, J. P. (2011, June). A Fully Automated Reconfigurable Calculation Engine Dedicated to the Real-Time Simulation of High Switching Frequency Power Electronic Circuits [Paper]. ELECTRIMACS 2011, Cergy-Pontoise, France. Published in Mathematics and Computers in Simulation, 91. External link
Ould-Bachir, T., & David, J. P. (2013). Self-alignment schemes for the implementation of addition-related floating-point operators. ACM Transactions on Reconfigurable Technology and Systems, 6(1), 1-21. External link
Ould-Bachir, T., Dufour, C., Bélanger, J., Mahseredjian, J., & David, J. P. (2012, May). Effective floating-point calculation engines intended for the FPGA-based HIL simulation [Paper]. 21st IEEE International Symposium on Industrial Electronics (ISIE 2012), Hangzhou, China. External link
Ould-Bachir, T., Dufour, C., David, J. P., & Mahseredjian, J. (2011, June). Floating-Point Engines for the FPGA-Based Real-Time Simulation of Power Electronic Circuits [Paper]. International Conference on Power Systems Transients (IPST 2011), Delft, Netherlands (7 pages). External link
Ould-Bachir, T., Dufour, C., David, J. P., Bélanger, J., & Mahseredjian, J. (2011, June). Reconfigurable floating-point engines for the real-time simulation of PECs: A high-speed PMSM drive case study [Paper]. International Conference on Modeling and Simulation of Electric Machines, Converters and Systems (ElectrIMACS 2011), Cergy-Pontoise, France. Unavailable
Ould-Bachir, T., David, J. P., Dufour, C., & Bélanger, J. (2010, November). Effective FPGA-based electric motor modeling with floating-point cores [Paper]. 36th Annual Conference of IEEE Industrial Electronics (IECON 2010), Glendale, Arizona, USA. External link
Ould-Bachir, T., & David, J. P. (2010, September). FPGA-Based Real-Time Simulation of State-Space Models using Floating-Point Cores [Paper]. 14th International Power Electronics and Motion Control Conference (EPE/PEMC 2010), Ohrid, Republic of Macedonia. External link
Ould-Bachir, T., & David, J. P. (2010, May). Performing floating-point Accumulation on a Modern FPGA in Single and Double Precision [Paper]. 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), Charlotte, North Carolina. External link
Ogoubi, E., & David, J. P. (2004, June). Automatic synthesis from high level ASM to VHDL: a case study [Paper]. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec. External link
Perdigon Romero, F., David, J. P., & Cohen-Adad, J. (2018, August). Vertebral labeling on MRI using deep learning techniques [Abstract]. NeuroInformatics 2018, Montréal, Qc, Canada. External link
Quisquater, J.-J., Standaert, F.-X., Rouvroy, G., David, J. P., & Legat, J.-D. (2002, September). A cryptanalytic time-memory tradeoff: first FPGA implementation [Paper]. 12th International Conference on Field Programmable Logic and Applications (FPL 2002), Montpellier, France. External link
Riviello, A., & David, J. P. (2019, September). Binary speech features for keyword spotting tasks [Paper]. 20th Annual Conference of the International Speech Communication Association: Crossroads of Speech and Language (INTERSPEECH 2019), Graz, Austria. External link
Su, M., David, J. P., Savaria, Y., Pontikakis, B., & Luinaud, T. (2022, May). An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. External link
Sanchez Correa, R., & David, J. P. (2018). Ultra-low latency communication channels for FPGA-based HPC cluster. Integration, 63, 41-55. External link
Saad, H., Dennetière, S., Mahseredjian, J., Ould-Bachir, T., & David, J. P. (2014). Simulation of transients for VSC-HVDC transmission systems based on modular multilevel converters. In Transient analysis of power systems (pp. 317-359). External link
Saint-Mleux, X., Feeley, M., & David, J. P. (2006, June). A scheme compiler for hardware dataflow machines [Paper]. Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2006), Ottawa, Canada (4 pages). Unavailable
Saint-Mleux, X., Feeley, M., & David, J. P. (2006, September). SHard: a scheme to hardware compiler [Paper]. Scheme and Functional Programming, Portland, OR (11 pages). Unavailable
Sun, L. P., Aboulhamid, E. M., & David, J. P. (2003, December). Network on chip using a reconfigurable platform [Paper]. 46th Midwest Symposium on Circuits and Systems (MWSCAS 2003), Cairo, Egypt. External link
Traore, M., Langlois, J. M. P., & David, J. P. (2022, June). ASIP accelerator for LUT-based neural networks inference [Paper]. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada. External link
Trigui, A., Ali, M., Hached, S., David, J. P., Ammari, A. C., Savaria, Y., & Sawan, M. (2020). Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(11), 3978-3990. External link
Trullemans-Anckaert, A.-M., Ferreira, R., David, J. P., & Legat, J.-D. (2000, November). A multi-FPGA system for prototyping power conscious algorithms [Paper]. 15th Design of Circuit and Integrated Systems Conference (DCIS 2000), Montpellier, France. Unavailable
Zeghaida, A.-A., Daultani, D., Langlois, J. M. P., & David, J. P. (2024, August). Scalable Low-Complexity Implementation of Constant Matrix Multiplication Circuits [Paper]. IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS 2024), Springfield, MA, USA. External link
Zerarka, M. T., David, J. P., & Aboulhamid, E. M. (2004, July). High speed emulation of gene regulatory networks using FPGAs [Paper]. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japan. External link
