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Low latency solver for linear equation systems in floating point arithmetic

Jean Pierre David

Paper (2015)

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Department: Department of Electrical Engineering
Research Center: GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL: https://publications.polymtl.ca/34775/
Conference Title: International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015)
Conference Location: Mexico City, Mexico
Conference Date(s): 2015-12-07 - 2015-12-09
Publisher: IEEE
DOI: 10.1109/reconfig.2015.7393326
Official URL: https://doi.org/10.1109/reconfig.2015.7393326
Date Deposited: 18 Apr 2023 15:06
Last Modified: 05 Apr 2024 11:26
Cite in APA 7: David, J. P. (2015, December). Low latency solver for linear equation systems in floating point arithmetic [Paper]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Mexico City, Mexico (7 pages). https://doi.org/10.1109/reconfig.2015.7393326

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