Mostafa Elbediwy, Bill Pontikakis, Jean Pierre David
and Yvon Savaria
Article (2023)
 Open Acess document in PolyPublie and at official publisher |
|
Open Access to the full text of this document Published Version Terms of Use: Creative Commons Attribution Download (1MB) |
| Department: | Department of Electrical Engineering |
|---|---|
| PolyPublie URL: | https://publications.polymtl.ca/54804/ |
| Journal Title: | IEEE Access (vol. 11) |
| Publisher: | IEEE |
| DOI: | 10.1109/access.2023.3286726 |
| Official URL: | https://doi.org/10.1109/access.2023.3286726 |
| Date Deposited: | 29 Aug 2023 16:17 |
| Last Modified: | 30 Sep 2024 10:41 |
| Cite in APA 7: | Elbediwy, M., Pontikakis, B., David, J. P., & Savaria, Y. (2023). A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access, 11, 61422-61436. https://doi.org/10.1109/access.2023.3286726 |
|---|---|
Statistics
Total downloads
Downloads per month in the last year
Origin of downloads
Dimensions
Repository Staff Only
|
View Item |
