A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA

M. Daigneault and Jean Pierre David

Paper (2010)

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Department:	Department of Electrical Engineering
Research Center:	GR2M - Microelectronics and Microsystems Research Group
PolyPublie URL:	https://publications.polymtl.ca/18446/
Conference Title:	8th IEEE International NEWCAS Conference (NEWCAS 2010)
Conference Location:	Montréal, Québec
Conference Date(s):	2010-06-20 - 2010-06-23
Publisher:	IEEE
DOI:	10.1109/newcas.2010.5603945
Official URL:	https://doi.org/10.1109/newcas.2010.5603945
Date Deposited:	18 Apr 2023 15:13
Last Modified:	05 Apr 2024 11:00

Cite in APA 7:	Daigneault, M., & David, J. P. (2010, June). A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA [Paper]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. https://doi.org/10.1109/newcas.2010.5603945
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