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Parallel hashing memories : an alternative to content addressable memories

P. Mahoney, Yvon Savaria, Guy Bois and P. Plante

Paper (2005)

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Additional Information: Nom historique du département: Département de génie informatique
Department: Department of Computer Engineering and Software Engineering
Department of Electrical Engineering
PolyPublie URL: https://publications.polymtl.ca/23901/
Conference Title: 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005)
Conference Location: Québec City, Que., Canada
Conference Date(s): 2005-06-19 - 2005-06-22
Publisher: IEEE
DOI: 10.1109/newcas.2005.1496691
Official URL: https://doi.org/10.1109/newcas.2005.1496691
Date Deposited: 18 Apr 2023 15:18
Last Modified: 05 May 2023 15:30
Cite in APA 7: Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (2005, June). Parallel hashing memories : an alternative to content addressable memories [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec City, Que., Canada. https://doi.org/10.1109/newcas.2005.1496691

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