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Items where Author is "Bois, Guy"

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Number of items: 94.

A

Al Sammane, G., Zaki, M. H., Tahar, S., & Bois, G. (2007, August). Constraint-based verification of delta-sigma modulators using interval analysis [Paper]. 50th Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montreal, Qc, Canada (4 pages). External link

B

Bois, G. (2018, January). Specific needs for the modelling and the refinement of CPU and FPGA platforms [Paper]. European Network on High Performance and Embedded Architecture and Compilation (HIPEAC 2018), Manchester, England. Unavailable

Bois, G., Guérard, H., & Jenn, E. (2017, June). Using virtual platforms for early architectural exploration : experimentation on an image processing system [Paper]. 54th Design Automation Conference (DAC 2017), Austin, Texas. External link

Bao, L., Bois, G., Boland, J.-F., & Savard, J. (2015). Model-based Method to Automate the Design of IMA Avionics System Based on Cosimulation. SAE International Journal of Aerospace, 8(2), 234-242. External link

Benyoussef, M., Boland, J.-F., Nicolescu, G., Bois, G., & Hugues, J. (2014, February). Design space exploration: bridging the gap between high-level models and virtual execution platforms [Paper]. Embedded Real Time System and Software Congress (ERTS2 2014), Toulouse, France (10 pages). External link

Bois, G. (2013, October). A Complete HW/SW Codesign flow for heterogeneous platforms [Paper]. Workshop on Many-Core Embedded Systems (MCES2013), Montréal, Québec. Unavailable

Bois, G. (2013, April). End-to-end automated HW/SW co-design for reconfigurable SoC [Paper]. Electronic Design Process Symposium (EDPS 2013), Monterey, Calif.. Unavailable

Boland, J.-F., Bois, G., & Oudet, J.-P. (2012, November). Novel methodologies to support the architectural exploration of safety-critical systems [Paper]. Recherche et Innovation pour les Transports du Futur (RITF 2012), Paris, France. Unavailable

Bois, G., Moss, L., Filion, L., & Fontaine, S. (2010). Codesign experiences based on a virtual platform. In Bailey, B., & Martin, G. (eds.), ESL models and their application : electronic system level design and verification practice (273-309). External link

Beucher, N., Belanger, N., Savaria, Y., & Bois, G. (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), 155-165. External link

Beucher, N., Belanger, N., Savaria, Y., & Bois, G. (2006, October). Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor [Paper]. IEEE Workshop on Signal Processing Systems Design and Implementation, Banff, AB, Canada. External link

Bois, G., Filion, L., Tsikhanovich, A., & Aboulhamid, E. M. (2004). Modélisation, raffinement et programmation orientée objet avec SystemC. In Spécification et validation des systèmes monopuces (171-208). External link

Benny, O., Rondonneau, M., Chevalier, J., Bois, G., Aboulhamid, E. M., & Boyer, F.-R. (2004, March). SoC software refinement approach for a systemC platform [Paper]. Design & Verification Conference & Exhibition (DVCon 2004), San Jose, California. Unavailable

Beaudin, S., Marceau, R. J., Bois, G., Savaria, Y., & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112. External link

Bissou, J. P., Dubois, M., Savaria, Y., & Bois, G. (2003, December). High-speed system bus for a SoC network processing platform [Paper]. 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt. External link

Bertola, M., & Bois, G. (2003, September). A methodology for the design of AHB bus master wrappers [Paper]. Euromicro Symposium on Digital System Design. External link

Bertola, M., & Bois, G. Teaching Bus Architectures With a Basic, Hands-on Soc Platform [Paper]. IEEE International Conference on Microelectronic Systems Education (MSE 2003). External link

Bosi, B., Bois, G., & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308. External link

Bois, G., Bosi, B., & Savaria, Y. (1997, January). High performance reconfigurable coprocessor for digital signal processing [Paper]. 14th Annual International Conference of the Mentor Graphics Users' Group, Portland, Oregon. Unavailable

Bois, G., & Cerny, E. (1996). Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(9), 1119-1126. External link

C

Carmel-Veilleux, T., Boland, J.-F., & Bois, G. (2011, May). A novel low-overhead flexible instrumentation framework for virtual platforms [Paper]. 22nd IEEE International Symposium on Rapid System Prototyping (RSP 2011), Karlsruhe, Germany. External link

Chevalier, J. M., De Nanclas, M., Filion, L., Benny, O., Rondonneau, M., Bois, G., & Aboulhamid, E. M. (2006). A Systemc Refinement Methodology for Embedded Software. IEEE Design & Test of Computers, 23(2), 148-158. External link

Cyr, G., Bois, G., & Aboulhamid, M. (2004). Generation of processor interface for SoC using standard communication protocol. IEE Proceedings. Computers and Digital Techniques, 151(5), 367-376. External link

Chevalier, J., Benny, O., Rondonneau, E. M., Bois, G., & Boyer, F.-R. (2004). SPACE : a hardware/software system C modeling platform including and RTOS. In Languages for System Specification : Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems, and Property Specification from FDL'03 (91-104). External link

Charest, L., Aboulhamid, M., & Bois, G. (2003). Applying multi-paradigm and patterns approaches to hardware/software design and reuse. In Patterns and skeletons for parallel and distributed computing (97-325). External link

Cerny, E., Bois, G., Bourgault, M., Demers, L.-P., Fauvel, S., Jacques, P., Mailhot, P., & Roy, C. (1989). Integration of VLSI CAD tools based on cell-objects : the CHESHIRE system. In Zobrist, G. W. (ed.), Progress in computer-aided VLSI Design : tools (235-272). External link

D

Dong, Z. J., Zaki, M. H., Sammane, G. A., Tahar, S., & Bois, G. (2007, December). Checking properties of PLL designs using run-time verification [Paper]. Internatonal Conference on Microelectronics (ICM 2007), Cairo, Egypt (4 pages). External link

Deslauriers, F., Langevin, M., Bois, G., Savaria, Y., & Paulin, P. (2006, June). RoC: a scalable network on chip based on the token ring concept [Paper]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. External link

Dubois, M., Savaria, Y., & Bois, G. (2005, April). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands [Paper]. IEEE SoutheastCon 2004, Fort Lauderdale, Florida, USA. External link

Dubois, M., Bois, G., & Savaria, Y. (2004). Double profiling methodology for video processing platform. WSEAS Transactions on Computers, 3(6), 1802-1807. Unavailable

F

Fontaine, S., Goyette, S., Langlois, J. M. P., & Bois, G. (2008, October). Acceleration of a 3D target tracking algorithm using an application specific instruction set processor [Paper]. IEEE International Conference on Computer Design (ICCD 2008). External link

Fontaine, S., Filion, L., & Bois, G. (2008, September). Exploring ISS abstractions for embedded software design [Paper]. 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2008). External link

Filion, L., Chevalier, J., Bois, G., & Aboulhamid, E. M. The Syslib-Picasso Methodology for the Co-Design Specification Capture Phase [Paper]. System-on-Chip for Real-Time Applications. External link

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Girard, S. R., Legault, V., Bois, G., & Boland, J.-F. (2019). Avionics graphics hardware performance prediction with machine learning. Scientific Programming, 2019, 1-15. Available

Gaudon, M., Bois, G., Hugues, J., & Monteiro, F. (2015, October). Performance verification for ESL design methodology from AADL models [Paper]. International Symposium on Rapid System Prototyping (RSP 2015), Amsterdam, Netherlands. External link

H

Hadjiat, K., St-Pierre, F., Bois, G., Savaria, Y., Langevin, M., & Paulin, P. (2007, December). An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco. External link

Heneault, Y., Filion, L., Bois, G., & Aboulhamid, E. M. A Fast Hardware Co-Specification and Co-Simulation Methodology Integrated in a H/S Co-Design Platform [Paper]. 13th International Conference on Microelectronics (ICM 2001). External link

J

Jenn, E., Monteiro, F., Bois, G., & Duplantier, K. (2017). Design space exploration : the image based monitoring case. In Modelling and formal verification in action : the INGEQUIP Project Team . Unavailable

K

Kroumba, S. M., Bois, G., & Savaria, Y. (1994, August). Synthesis approach for the generation of parallel architectures [Paper]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. External link

L

Lacroix, A. B., Langlois, J. M. P., Boyer, F.-R., Gosselin, A., & Bois, G. (2016, March). Node configuration for the Aho-Corasick algorithm in intrusion detection systems [Poster]. ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, Californie (2 pages). Available

Landry, K., Boland, J.-F., & Bois, G. (2015, September). Integration and Performances Analysis of a Data Distribution Service Middleware in Avionics [Paper]. SAE AeroTech Congress and Exhibition (AEROTECH 2015), Seattle, WA, United states. External link

Le Beux, S., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2013). Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems, 37(1), 87-98. External link

Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2011, March). Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology [Paper]. 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France. External link

Le Beux, S., Bois, G., Nicolescu, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (2010). Combining mapping and partitioning exploration for NoC-based embedded systems. Journal of Systems Architecture, 56(7), 223-232. External link

Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80. External link

Le Beux, S., Nicolescu, G., Bois, G., & Paulin, P. (2010, May). A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. External link

Le Beux, S., Nicolescu, G., Bois, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (2009, July). Optimizing configuration and application mapping for MPSoC architectures [Paper]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2009), San Francisco, California. External link

Lapalme, J., Aboulhamed, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (2004, June). Esys.net: A New Solution for Embedded Systems Modeling and Simulation [Paper]. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C.. Published in ACM Sigplan Notices, 39(7). External link

Lapalme, J., Aboulhamid, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (2004, February). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France. External link

Lemire, J. F., Aboulhamid, E. M., Savaria, Y., Bois, G., & Baron, A. (2003, January). Implementing e assertion checkers from an SDL executable specifications [Paper]. DVCON, San José, USA. Unavailable

Le Chapelain, B., Mechain, A., Savaria, Y., & Bois, G. (1999, May). Development of a high performance TSPC library for implementation of large digital building blocks [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. External link

Lejmi, S., Bois, G., & Savaria, Y. (1996, January). On the effects of retiming applied to self-checking sequential circuit [Paper]. 2nd IEEE On-Line Testing Workshop, Biarritz. Unavailable

M

Montero, F., Bois, G., Jenn, E., & Duplantier, K. (2016, August). Architectural exploration and implementation of an image processing chain with SpaceStudio [Paper]. 26th International Conference on Field Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland (1 page). External link

Moss, L., Guerard, H., Dare, G., & Bois, G. (2012, October). An ESL methodology for rapid creation of embedded aerospace systems using hardware-software co-design on virtual platforms [Paper]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ (10 pages). External link

Moss, L., & Bois, G. (2009). On the Scott-continuity of tagged signal processes. (Technical Report n° EPM-RT-2009-01). Available

Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (2009). Performance characterization for the implementation of content addressable memories based on parallel hashing memories. In Transactions on High-Performance Embedded Architectures and Compilers. II (Vol. 5470, 307-325). External link

Moss, L., Cantin, M.-A., Bois, G., & Mostapha Aboulhamid, E. (2008, June). Automation of communication refinement and hardware synthesis within a system-level design methodology [Paper]. 19th IEEE/IFIP International Symposium on Rapid System Prototyping. External link

Moss, L., De Nanclas, M., Filion, L., Fontaine, S., Bois, G., & Aboulhamid, M. (2007, April). Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice Acropolis, France. External link

Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (2005, June). Parallel hashing memories : an alternative to content addressable memories [Paper]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec City, Que., Canada. External link

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Nsame, P., Bois, G., & Savaria, Y. (2015, May). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platforms [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal. External link

Nsame, P., Bois, G., & Savaria, Y. (2014, August). Adaptive real-time DSP acceleration for SoC applications [Paper]. 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX. External link

Nsame, P., Bois, G., & Savaria, Y. (2014, December). A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT [Paper]. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France. External link

Nsame, P., Bois, G., & Savaria, Y. (2014, May). Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications [Paper]. IEEE 23rd North Atlantic Test Workshop (NATW 2014), Johnson City, NY, USA (4 pages). External link

Nekili, M., Savaria, Y., & Bois, G. (2001, May). Minimizing process-induced skew using elay tuning [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie. External link

Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. External link

Nekili, M., Savaria, Y., Bois, G., Bayoumi, M. A., & Jullien, G. (1998, February). Design of clock distribution networks in presence of process variations [Paper]. 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA. External link

Nekili, M., Bois, G., & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. External link

Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Technical Report n° EPM-RT-94-09). Restricted access

Nekili, M., Savaria, Y., & Bois, G. (1994, January). Fast low-power driver for long interconnections in VLSI systems [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), Londres. External link

Nekili, M., Savaria, Y., & Bois, G. (1994, August). A variable-size parallel regenerator for long integrated interconnections [Paper]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. External link

P

Posso, J., Bois, G., & Savaria, Y. (2022, May). Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. External link

Pollina, M., Leclerc, Y., Conquet, E., Bois, G., & Moss, L. (2012, February). The Assert Set of Tools for Engineering (TASTE): demonstrator, HW/SW codesign and future evolution [Paper]. Embedded Real Time Software and Systems (ERTS2 2012), Toulouse, France (4 pages). Unavailable

Pollina, M., Leclerc, Y., Conquet, E., Perrotin, M., Bois, G., & Moss, L. (2011, May). The Assert Set of Tools for Engineering (TASTE): current features, demonstrator and future evolution [Paper]. DAta Systems In Aerospace (DASIA 2011), San Anton, Malta (5 pages). External link

Provost, S., Lavigueur, B., Bois, G., & Nicolescu, G. Integration of Configurable Processors in a Multiprocessor Platform [Paper]. IEEE International SOC Conference (SOCC 2006). External link

Pera, F., Savaria, Y., & Bois, G. (1997, June). Time delay measurement methods for integrated transmission lines and high speed cells characterization [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong. External link

Q

Quinn, D., Lavigueur, B., Bois, G., & Aboulhamid, M. (2004, February). A system level exploration platform and methodology for network applications based on configurable processors [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France. External link

R

Rogers-Vallée, M., Cantin, M.-A., Moss, L., & Bois, G. (2010, October). IP characterization methodology for fast and accurate power consumption estimation at transactional level model [Paper]. IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, Netherlands. External link

Regimbal, S., Savaria, Y., & Bois, G. (2004, July). Verification strategy determination using dependence analysis of transaction-level models [Paper]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. External link

Regimbal, S., Lemire, J. F., Savaria, Y., Bois, G., Aboulhamid, M., & Baron, A. (2002, July). Aspect Partitioning for Hardware Verification Reuse [Paper]. System-on-Chip for Real-Time Applications. External link

Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E. M., & Baron, A. (2003, June). Automating functional coverage analysis based on an executable specification [Paper]. 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications. External link

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Savard, J., Bao, L., Bois, G., & Boland, J.-F. (2013, September). Model-based design flow driven by integrated modular avionic simulations [Paper]. SAE AeroTech Congress and Exhibition (AEROTECH 2013), Montréal, Québec. External link

Shaditalab, M., Bois, G., Sawan, M., Pocek, K. L., & Arnold, J. M. (1998, April). Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks [Paper]. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA. External link

Savaria, Y., Bois, G., Popovic, P., & Wayne, A. Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems [Paper]. High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic. External link

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Tsikhanovich, A., Aboulhamid, E. M., & Bois, G. (2009). Timing Specification in Transaction Level Models. In Aboulhamid, E. M., & Rousseau, F. (eds.), System Level Design with .Net Technology (203-238). External link

Thibeault, J. F., Hubin, M., Deslauriers, F., Samson, P., & Bois, G. (2005, June). A Reprogrammable Soc Design for a Real-Time Control Application [Paper]. IEEE International Conference on Microelectronic Systems Education (MSE 2005), Anaheim, California, USA. External link

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Vakili, S., Langlois, J. M. P., & Bois, G. (2016). Accuracy-aware processor customisation for fixed-point arithmetic. IET Computers and Digital Techniques, 10(1), 1-11. External link

Vakili, S., Langlois, J. M. P., & Bois, G. (2015, June). Designing Customized Microprocessors for Fixed-Point Computation [Paper]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec. External link

Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Customised soft processor design: A compromise between architecture description languages and parameterisable processors. IET Computers and Digital Techniques, 7(3), 122-131. External link

Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(12), 1853-1865. External link

Vakili, S., Langlois, J. M. P., & Bois, G. (2013, May). Finite-precision error modeling using affine arithmetic [Paper]. 38th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013), Vancouver, BC, Canada. External link

Vakili, S., Gil, D. C., Langlois, J. M. P., Savaria, Y., & Bois, G. (2011, December). Customized embedded processor design for global photographic tone mapping [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link

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Zaki, M. H., Denman, W., Tahar, S., & Bois, G. (2009). Integrating abstraction techniques for formal verification of analog designs. Journal of Aerospace Computing, Information and Communication, 6(5), 373-392. External link

Zaki, M. H., Tahar, S., & Bois, G. (2008). Formal verification of analog and mixed signal designs: A survey. Microelectronics Journal, 39(12), 1395-1404. External link

Zaki, M. H., Al-Sammane, G., Tahar, S., & Bois, G. (2007, November). Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs [Paper]. Formal Methods in Computer Aided Design (FMCAD 2007), Austin, TX, USA (9 pages). External link

List generated on: Fri Apr 12 07:31:02 2024 EDT