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Guy BoisDépartement de génie informatique et génie logiciel
Voir sa fiche dans le Répertoire des Expertises de Polytechnique Montréal
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Al Sammane, G., Zaki, M. H., Tahar, S., & Bois, G. (août 2007). Constraint-based verification of delta-sigma modulators using interval analysis [Communication écrite]. 50th Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montreal, Qc, Canada (4 pages). Lien externe
Bois, G. (janvier 2018). Specific needs for the modelling and the refinement of CPU and FPGA platforms [Communication écrite]. European Network on High Performance and Embedded Architecture and Compilation (HIPEAC 2018), Manchester, England. Non disponible
Bois, G., Guérard, H., & Jenn, E. (juin 2017). Using virtual platforms for early architectural exploration : experimentation on an image processing system [Communication écrite]. 54th Design Automation Conference (DAC 2017), Austin, Texas. Lien externe
Bao, L., Bois, G., Boland, J.-F., & Savard, J. (2015). Model-based Method to Automate the Design of IMA Avionics System Based on Cosimulation. SAE International Journal of Aerospace, 8(2), 234-242. Lien externe
Benyoussef, M., Boland, J.-F., Nicolescu, G., Bois, G., & Hugues, J. (février 2014). Design space exploration: bridging the gap between high-level models and virtual execution platforms [Communication écrite]. Embedded Real Time System and Software Congress (ERTS2 2014), Toulouse, France (10 pages). Lien externe
Bois, G. (octobre 2013). A Complete HW/SW Codesign flow for heterogeneous platforms [Communication écrite]. Workshop on Many-Core Embedded Systems (MCES2013), Montréal, Québec. Non disponible
Bois, G. (avril 2013). End-to-end automated HW/SW co-design for reconfigurable SoC [Communication écrite]. Electronic Design Process Symposium (EDPS 2013), Monterey, Calif.. Non disponible
Boland, J.-F., Bois, G., & Oudet, J.-P. (novembre 2012). Novel methodologies to support the architectural exploration of safety-critical systems [Communication écrite]. Recherche et Innovation pour les Transports du Futur (RITF 2012), Paris, France. Non disponible
Bois, G., Moss, L., Filion, L., & Fontaine, S. (2010). Codesign experiences based on a virtual platform. Dans Bailey, B., & Martin, G. (édit.), ESL models and their application : electronic system level design and verification practice (p. 273-309). Lien externe
Beucher, N., Belanger, N., Savaria, Y., & Bois, G. (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), 155-165. Lien externe
Beucher, N., Belanger, N., Savaria, Y., & Bois, G. (octobre 2006). Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor [Communication écrite]. IEEE Workshop on Signal Processing Systems Design and Implementation, Banff, AB, Canada. Lien externe
Bois, G., Filion, L., Tsikhanovich, A., & Aboulhamid, E. M. (2004). Modélisation, raffinement et programmation orientée objet avec SystemC. Dans Spécification et validation des systèmes monopuces (p. 171-208). Lien externe
Benny, O., Rondonneau, M., Chevalier, J., Bois, G., Aboulhamid, E. M., & Boyer, F.-R. (mars 2004). SoC software refinement approach for a systemC platform [Communication écrite]. Design & Verification Conference & Exhibition (DVCon 2004), San Jose, California. Non disponible
Beaudin, S., Marceau, R. J., Bois, G., Savaria, Y., & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112. Lien externe
Bissou, J. P., Dubois, M., Savaria, Y., & Bois, G. (décembre 2003). High-speed system bus for a SoC network processing platform [Communication écrite]. 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt. Lien externe
Bertola, M., & Bois, G. (septembre 2003). A methodology for the design of AHB bus master wrappers [Communication écrite]. Euromicro Symposium on Digital System Design. Lien externe
Bertola, M., & Bois, G. Teaching Bus Architectures With a Basic, Hands-on Soc Platform [Communication écrite]. IEEE International Conference on Microelectronic Systems Education (MSE 2003). Lien externe
Bosi, B., Bois, G., & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308. Lien externe
Bois, G., Bosi, B., & Savaria, Y. (janvier 1997). High performance reconfigurable coprocessor for digital signal processing [Communication écrite]. 14th Annual International Conference of the Mentor Graphics Users' Group, Portland, Oregon. Non disponible
Bois, G., & Cerny, E. (1996). Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(9), 1119-1126. Lien externe
Carmel-Veilleux, T., Boland, J.-F., & Bois, G. (mai 2011). A novel low-overhead flexible instrumentation framework for virtual platforms [Communication écrite]. 22nd IEEE International Symposium on Rapid System Prototyping (RSP 2011), Karlsruhe, Germany. Lien externe
Chevalier, J. M., De Nanclas, M., Filion, L., Benny, O., Rondonneau, M., Bois, G., & Aboulhamid, E. M. (2006). A Systemc Refinement Methodology for Embedded Software. IEEE Design & Test of Computers, 23(2), 148-158. Lien externe
Cyr, G., Bois, G., & Aboulhamid, M. (2004). Generation of processor interface for SoC using standard communication protocol. IEE Proceedings. Computers and Digital Techniques, 151(5), 367-376. Lien externe
Chevalier, J., Benny, O., Rondonneau, E. M., Bois, G., & Boyer, F.-R. (2004). SPACE : a hardware/software system C modeling platform including and RTOS. Dans Languages for System Specification : Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems, and Property Specification from FDL'03 (p. 91-104). Lien externe
Charest, L., Aboulhamid, M., & Bois, G. (2003). Applying multi-paradigm and patterns approaches to hardware/software design and reuse. Dans Patterns and skeletons for parallel and distributed computing (p. 97-325). Lien externe
Cerny, E., Bois, G., Bourgault, M., Demers, L.-P., Fauvel, S., Jacques, P., Mailhot, P., & Roy, C. (1989). Integration of VLSI CAD tools based on cell-objects : the CHESHIRE system. Dans Zobrist, G. W. (édit.), Progress in computer-aided VLSI Design : tools (p. 235-272). Lien externe
Dong, Z. J., Zaki, M. H., Sammane, G. A., Tahar, S., & Bois, G. (décembre 2007). Checking properties of PLL designs using run-time verification [Communication écrite]. International Conference on Microelectronics (ICM 2007), Cairo, Egypt (4 pages). Lien externe
Deslauriers, F., Langevin, M., Bois, G., Savaria, Y., & Paulin, P. (juin 2006). RoC: a scalable network on chip based on the token ring concept [Communication écrite]. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Lien externe
Dubois, M., Savaria, Y., & Bois, G. (avril 2005). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands [Communication écrite]. IEEE SoutheastCon 2004, Fort Lauderdale, Florida, USA. Lien externe
Dubois, M., Bois, G., & Savaria, Y. (2004). Double profiling methodology for video processing platform. WSEAS Transactions on Computers, 3(6), 1802-1807. Non disponible
Fontaine, S., Goyette, S., Langlois, J. M. P., & Bois, G. (octobre 2008). Acceleration of a 3D target tracking algorithm using an application specific instruction set processor [Communication écrite]. IEEE International Conference on Computer Design (ICCD 2008). Lien externe
Fontaine, S., Filion, L., & Bois, G. (septembre 2008). Exploring ISS abstractions for embedded software design [Communication écrite]. 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2008). Lien externe
Filion, L., Chevalier, J., Bois, G., & Aboulhamid, E. M. The Syslib-Picasso Methodology for the Co-Design Specification Capture Phase [Communication écrite]. System-on-Chip for Real-Time Applications. Lien externe
Girard, S. R., Legault, V., Bois, G., & Boland, J.-F. (2019). Avionics graphics hardware performance prediction with machine learning. Scientific Programming, 2019, 1-15. Disponible
Gaudon, M., Bois, G., Hugues, J., & Monteiro, F. (octobre 2015). Performance verification for ESL design methodology from AADL models [Communication écrite]. International Symposium on Rapid System Prototyping (RSP 2015), Amsterdam, Netherlands. Lien externe
Hadjiat, K., St-Pierre, F., Bois, G., Savaria, Y., Langevin, M., & Paulin, P. (décembre 2007). An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept [Communication écrite]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco. Lien externe
Heneault, Y., Filion, L., Bois, G., & Aboulhamid, E. M. A Fast Hardware Co-Specification and Co-Simulation Methodology Integrated in a H/S Co-Design Platform [Communication écrite]. 13th International Conference on Microelectronics (ICM 2001). Lien externe
Jenn, E., Monteiro, F., Bois, G., & Duplantier, K. (2017). Design space exploration : the image based monitoring case. Dans Modelling and formal verification in action : the INGEQUIP Project Team . Non disponible
Kroumba, S. M., Bois, G., & Savaria, Y. (août 1994). Synthesis approach for the generation of parallel architectures [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Lacroix, A. B., Langlois, J. M. P., Boyer, F.-R., Gosselin, A., & Bois, G. (mars 2016). Node configuration for the Aho-Corasick algorithm in intrusion detection systems [Affiche]. ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, Californie (2 pages). Disponible
Landry, K., Boland, J.-F., & Bois, G. (septembre 2015). Integration and Performances Analysis of a Data Distribution Service Middleware in Avionics [Communication écrite]. SAE AeroTech Congress and Exhibition (AEROTECH 2015), Seattle, WA, United states. Lien externe
Le Beux, S., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2013). Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems, 37(1), 87-98. Lien externe
Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (mars 2011). Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology [Communication écrite]. 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France. Lien externe
Le Beux, S., Bois, G., Nicolescu, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (2010). Combining mapping and partitioning exploration for NoC-based embedded systems. Journal of Systems Architecture, 56(7), 223-232. Lien externe
Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G., & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80. Lien externe
Le Beux, S., Nicolescu, G., Bois, G., & Paulin, P. (mai 2010). A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France. Lien externe
Le Beux, S., Nicolescu, G., Bois, G., Bouchebaba, Y., Langevin, M., & Paulin, P. (juillet 2009). Optimizing configuration and application mapping for MPSoC architectures [Communication écrite]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2009), San Francisco, California. Lien externe
Lapalme, J., Aboulhamed, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (juin 2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation [Communication écrite]. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C.. Publié dans ACM Sigplan Notices, 39(7). Lien externe
Lapalme, J., Aboulhamid, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (février 2004). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France. Lien externe
Lemire, J. F., Aboulhamid, E. M., Savaria, Y., Bois, G., & Baron, A. (février 2003). Implementing e assertion checkers from an SDL executable specifications [Communication écrite]. DVCON, San José, USA. Non disponible
Le Chapelain, B., Mechain, A., Savaria, Y., & Bois, G. (mai 1999). Development of a high performance TSPC library for implementation of large digital building blocks [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA. Lien externe
Lejmi, S., Bois, G., & Savaria, Y. (janvier 1996). On the effects of retiming applied to self-checking sequential circuit [Communication écrite]. 2nd IEEE On-Line Testing Workshop, Biarritz. Non disponible
Montero, F., Bois, G., Jenn, E., & Duplantier, K. (août 2016). Architectural exploration and implementation of an image processing chain with SpaceStudio [Communication écrite]. 26th International Conference on Field Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland (1 page). Lien externe
Moss, L., Guerard, H., Dare, G., & Bois, G. (octobre 2012). An ESL methodology for rapid creation of embedded aerospace systems using hardware-software co-design on virtual platforms [Communication écrite]. SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ (10 pages). Lien externe
Moss, L., & Bois, G. (2009). On the Scott-continuity of tagged signal processes. (Rapport technique n° EPM-RT-2009-01). Disponible
Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (2009). Performance characterization for the implementation of content addressable memories based on parallel hashing memories. Dans Transactions on High-Performance Embedded Architectures and Compilers. II (Vol. 5470, p. 307-325). Lien externe
Moss, L., Cantin, M.-A., Bois, G., & Mostapha Aboulhamid, E. (juin 2008). Automation of communication refinement and hardware synthesis within a system-level design methodology [Communication écrite]. 19th IEEE/IFIP International Symposium on Rapid System Prototyping. Lien externe
Moss, L., De Nanclas, M., Filion, L., Fontaine, S., Bois, G., & Aboulhamid, M. (avril 2007). Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice Acropolis, France. Lien externe
Mahoney, P., Savaria, Y., Bois, G., & Plante, P. (juin 2005). Parallel hashing memories : an alternative to content addressable memories [Communication écrite]. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, QC, Canada. Lien externe
Nsame, P., Bois, G., & Savaria, Y. (mai 2015). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platforms [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal. Lien externe
Nsame, P., Bois, G., & Savaria, Y. (août 2014). Adaptive real-time DSP acceleration for SoC applications [Communication écrite]. 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX. Lien externe
Nsame, P., Bois, G., & Savaria, Y. (décembre 2014). A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT [Communication écrite]. 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France. Lien externe
Nsame, P., Bois, G., & Savaria, Y. (mai 2014). Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications [Communication écrite]. IEEE 23rd North Atlantic Test Workshop (NATW 2014), Johnson City, NY, USA (4 pages). Lien externe
Nekili, M., Savaria, Y., & Bois, G. (mai 2001). Minimizing process-induced skew using delay tuning [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. Lien externe
Nekili, M., Savaria, Y., Bois, G., Bayoumi, M. A., & Jullien, G. (février 1998). Design of clock distribution networks in presence of process variations [Communication écrite]. 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA. Lien externe
Nekili, M., Bois, G., & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. Lien externe
Nekili, M., Bois, G., & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid h-trees. (Rapport technique n° EPM-RT-94-09). Accès restreint
Nekili, M., Savaria, Y., & Bois, G. (mai 1994). Fast low-power driver for long interconnections in VLSI systems [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, UK. Lien externe
Nekili, M., Savaria, Y., & Bois, G. (août 1994). A variable-size parallel regenerator for long integrated interconnections [Communication écrite]. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA. Lien externe
Portas, F., Bois, G., & Savaria, Y. (juin 2024). CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign [Communication écrite]. 22nd IEEE Interregional NEWCAS Conference (NEWCAS 2024), Sherbrooke, QC, Canada. Lien externe
Posso, J., Bois, G., & Savaria, Y. (juin 2024). Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC [Communication écrite]. 22nd IEEE Interregional NEWCAS Conference (NEWCAS 2024), Sherbrooke, QC, Canada. Lien externe
Posso, J., Bois, G., & Savaria, Y. (mai 2022). Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA. Lien externe
Pollina, M., Leclerc, Y., Conquet, E., Bois, G., & Moss, L. (février 2012). The Assert Set of Tools for Engineering (TASTE): demonstrator, HW/SW codesign and future evolution [Communication écrite]. Embedded Real Time Software and Systems (ERTS2 2012), Toulouse, France (4 pages). Non disponible
Pollina, M., Leclerc, Y., Conquet, E., Perrotin, M., Bois, G., & Moss, L. (mai 2011). The Assert Set of Tools for Engineering (TASTE): current features, demonstrator and future evolution [Communication écrite]. DAta Systems In Aerospace (DASIA 2011), San Anton, Malta (5 pages). Lien externe
Provost, S., Lavigueur, B., Bois, G., & Nicolescu, G. Integration of Configurable Processors in a Multiprocessor Platform [Communication écrite]. IEEE International SOC Conference (SOCC 2006). Lien externe
Pera, F., Savaria, Y., & Bois, G. (juin 1997). Time delay measurement methods for integrated transmission lines and high speed cells characterization [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong. Lien externe
Quinn, D., Lavigueur, B., Bois, G., & Aboulhamid, M. (février 2004). A system level exploration platform and methodology for network applications based on configurable processors [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France. Lien externe
Rogers-Vallée, M., Cantin, M.-A., Moss, L., & Bois, G. (octobre 2010). IP characterization methodology for fast and accurate power consumption estimation at transactional level model [Communication écrite]. IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, Netherlands. Lien externe
Regimbal, S., Savaria, Y., & Bois, G. (juillet 2004). Verification strategy determination using dependence analysis of transaction-level models [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada. Lien externe
Regimbal, S., Lemire, J. F., Savaria, Y., Bois, G., Aboulhamid, M., & Baron, A. (juillet 2002). Aspect Partitioning for Hardware Verification Reuse [Communication écrite]. System-on-Chip for Real-Time Applications. Lien externe
Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E. M., & Baron, A. (juin 2003). Automating functional coverage analysis based on an executable specification [Communication écrite]. 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications. Lien externe
Savard, J., Bao, L., Bois, G., & Boland, J.-F. (septembre 2013). Model-based design flow driven by integrated modular avionic simulations [Communication écrite]. SAE AeroTech Congress and Exhibition (AEROTECH 2013), Montréal, Québec. Lien externe
Shaditalab, M., Bois, G., Sawan, M., Pocek, K. L., & Arnold, J. M. (avril 1998). Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks [Communication écrite]. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA. Lien externe
Savaria, Y., Bois, G., Popovic, P., & Wayne, A. Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems [Communication écrite]. High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic. Lien externe
Tsikhanovich, A., Aboulhamid, E. M., & Bois, G. (2009). Timing Specification in Transaction Level Models. Dans Aboulhamid, E. M., & Rousseau, F. (édit.), System Level Design with .Net Technology (p. 203-238). Lien externe
Thibeault, J.-F., Hubin, M., Deslauriers, F., Samson, P., & Bois, G. (juin 2005). A Reprogrammable Soc Design for a Real-Time Control Application [Communication écrite]. IEEE International Conference on Microelectronic Systems Education (MSE 2005), Anaheim, California, USA. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (2016). Accuracy-aware processor customisation for fixed-point arithmetic. IET Computers and Digital Techniques, 10(1), 1-11. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (juin 2015). Designing Customized Microprocessors for Fixed-Point Computation [Communication écrite]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Customised soft processor design: A compromise between architecture description languages and parameterisable processors. IET Computers and Digital Techniques, 7(3), 122-131. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (2013). Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(12), 1853-1865. Lien externe
Vakili, S., Langlois, J. M. P., & Bois, G. (mai 2013). Finite-precision error modeling using affine arithmetic [Communication écrite]. 38th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013), Vancouver, BC, Canada. Lien externe
Vakili, S., Gil, D. C., Langlois, J. M. P., Savaria, Y., & Bois, G. (décembre 2011). Customized embedded processor design for global photographic tone mapping [Communication écrite]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. Lien externe
Zaki, M. H., Denman, W., Tahar, S., & Bois, G. (2009). Integrating abstraction techniques for formal verification of analog designs. Journal of Aerospace Computing, Information and Communication, 6(5), 373-392. Lien externe
Zaki, M. H., Tahar, S., & Bois, G. (2008). Formal verification of analog and mixed signal designs: A survey. Microelectronics Journal, 39(12), 1395-1404. Lien externe
Zaki, M. H., Al-Sammane, G., Tahar, S., & Bois, G. (novembre 2007). Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs [Communication écrite]. Formal Methods in Computer Aided Design (FMCAD 2007), Austin, TX, USA (9 pages). Lien externe
