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Bensalem, H., Blaquière, Y., & Savaria, Y. (2023). An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(3), 1144-1148. External link
Bensalem, H., Blaquière, Y., & Savaria, Y. (2021, May). Acceleration of the secure hash algorithm-256 (SHA-256) on an FPGA-CPU cluster using OpenCL [Paper]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2021). Ring-Oscillator Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays. IEEE Transactions on Instrumentation and Measurement, 70, 1-10. External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2020). Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA. IET Circuits Devices & Systems, 14(8), 1243-1252. External link
Bensalem, H., Blaquière, Y., & Savaria, Y. (2019, May). Toward in-system monitoring of OpenCL-based designs on FPGA [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). External link
Darvishi, M., Audet, Y., & Blaquière, Y. (2018). Delay monitor circuit and delay change measurement due to SEU in SRAM-based FPGA. IEEE Transactions on Nuclear Science, 65(5), 1153-1160. External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2018). Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integration, 62, 159-169. External link
Lepercq, É., Blaquière, Y., & Savaria, Y. (2018). A pattern-based routing algorithm for a novel electronic system prototyping platform. Integration, 62, 224-237. External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2017, May). A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD (4 pages). External link
Berrima, S., Blaquière, Y., & Savaria, Y. (2017, August). Sub-ps resolution programmable delays implemented in a Xilinx FPGA [Paper]. 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Boston, MA. External link
Hussain, W., Fakhoury, H., Desgreys, P., Blaquière, Y., & Savaria, Y. (2016). An asynchronous delta-modulator based A/D converter for an electronic system prototyping platform. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(6), 751-762. External link
Hussain, W., Savaria, Y., & Blaquière, Y. (2016, May). A compact spatially configurable differential input stage for a field programmable interconnection network [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, Québec. External link
Hussain, W., Valorge, O., Blaquière, Y., & Savaria, Y. (2016). A novel spatially configurable differential interface for an electronic system prototyping platform. Integration, the VLSI Journal, 55, 129-137. External link
Guillemot, M., Nguyen, H., Bougataya, M., Blaquière, Y., Lakhssassi, A., Shields, M., & Savaria, Y. (2016). Wafer-scale rapid electronic systems prototyping platform: User support tools and thermo-mechanical validation. In Novel Advances in Microsystems Technologies and Their Applications (pp. 67-100). External link
Laflamme-Mayer, N., Blaquière, Y., & Sawan, M. (2015). A configurable analog buffer dedicated to a wafer-scale prototyping platform. Analog Integrated Circuits and Signal Processing, 82(1), 57-66. External link
Sion, G., Blaquière, Y., & Savaria, Y. (2015, July). Defect diagnosis algorithms for a field programmable interconnect network embedded in a very large area integrated circuit [Paper]. 21st International On-Line Testing Symposium (IOLTS 2015), Athena Pallas, Greece. External link
Darvishi, M., Audet, Y., Blaquière, Y., Thibeault, C., Pichette, S., & Tazi, F. Z. (2014). Circuit level modeling of extra combinational delays in SRAM-based FPGAs due to transient ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3535-3542. External link
Laflamme-Mayer, N., Blaquière, Y., Savaria, Y., & Sawan, M. (2014). A configurable multi-rail power and I/O pad applied to wafer-scale systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(11), 3135-3144. External link
Blaquière, Y., Basile-Bellavance, Y., Berrima, S., & Savaria, Y. (2014, June). Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, VIC, Australia (4 pages). External link
Laflamme-Mayer, N., Sawan, M., & Blaquière, Y. (2013, February). A configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems [Paper]. 4th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2013), Cusco, Peru. External link
Laflamme-Mayer, N., André, W., Valorge, O., Blaquière, Y., & Sawan, M. (2013). Configurable input-output power pad for wafer-scale microelectronic systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(11), 2024-2033. External link
Hussain, W., Savaria, Y., & Blaquière, Y. (2013, May). An interface for the I2C protocol in the WaferBoard TM [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, Chine. External link
Baratli, K., Lakhssassi, A., Blaquière, Y., & Savaria, Y. (2013, June). A netlist pruning tool for an electronic system prototyping platform [Paper]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. External link
Guillemot, M., Blaquière, Y., & Savaria, Y. (2013, May). Software Rendering Methods to Display Wafer Scale Integrated Circuit Dataset [Paper]. 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2013), Regina, Sask, CAN. External link
Nguyen, H. H., Guillemot, M., Savaria, Y., & Blaquière, Y. (2012, October). A new approach for pin detection for an electronic system prototyping reconfigurable platform [Paper]. 23rd IEEE International Symposium on Rapid System Prototyping (RSP 2012), Tampere, Finland. External link
Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquière, Y., Moupfouma, F., & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65. External link
Al-Terkawi Hasib, O., André, W., Blaquière, Y., & Savaria, Y. (2012, May). Propagating analog signals through a fully digital network on an electronic system prototyping platform [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of. External link
Laflamme-Mayer, N., Sawan, M., & Blaquière, Y. (2011, June). A dual-power rail, low-dropout, fast-response linear regulator dedicated to a wafer-scale electronic systems prototyping platform [Paper]. 9th IEEE International New Circuits and Systems Conference (NEWCAS 2011), Bordeaux, France. External link
Diop, M. D., Radji, M., André, W., Blaquière, Y., Hamoui, A. A., & Izquierdo, R. (2010, October). Electrical characterization of annular through silicon vias for a reconfigurable wafer-sized circuit board [Paper]. IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, Austin, TX, United states. External link
Laflamme-Mayer, N., Blaquière, Y., & Sawan, M. (2011, December). A large range and fine tuning configurable Bandgap reference dedicated to wafer-scale systems [Paper]. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon. External link
Valorge, O., André, W., Savaria, Y., & Blaquière, Y. (2011, June). Power supply analysis of a large area integrated circuit [Paper]. 9th IEEE International New Circuits and Systems Conference (NEWCAS 2011), Bordeaux, France. External link
Laflamme-Mayer, N., Valorge, O., Blaquière, Y., & Sawan, M. (2010, June). A Low-Power, Small-Area Voltage Reference Array for a Wafer-Scale Prototyping Platform [Paper]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. External link
Valorge, O., Blaquière, Y., & Savaria, Y. (2010, December). A spatially reconfigurable fast differential interface for a wafer scale configurable platform [Paper]. 17th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2010), Athens, Greece. External link
Berriah, O., Bougataya, M., Lakhssassi, A., Blaquière, Y., & Savaria, Y. (2010, June). Thermal analysis of a miniature electronic power device matched to a silicon wafer [Paper]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec. External link
Bougataya, M., Berriah, O., Lakhssassi, A., Dahmane, A.-O., Blaquière, Y., Savaria, Y., Norman, R., & Prytula, R. (2010, December). Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit [Paper]. 17th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece. External link
Basile-Bellavance, Y., Blaquière, Y., & Savaria, Y. (2009, June). Faults diagnosis methodology for the WaferNet interconnection network [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. External link
Lepercq, É., Valorege, O., Basile-Bellavance, Y., Laflamme-Mayer, N., Blaquière, Y., & Savaria, Y. (2009, October). An interconnection network for a novel reconfigurable circuit board [Paper]. 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada. External link
Lepercq, É., Blaquière, Y., Norman, R., & Savaria, Y. (2009, May). Workflow for an electronic configurable prototyping system [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan. External link
Norman, R., Valorge, O., Blaquière, Y., Lepercq, É., Basile-Bellavance, Y., El-Alaoui, Y., Prytula, R., & Savaria, Y. (2008, June). An active reconfigurable circuit board [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, QC, Canada. External link
Valorge, O., Nguyen, A. T., Blaquière, Y., Norman, R., & Savaria, Y. (2008, August). Digital signal propagation on a wafer-scale smart active programmable interconnect [Paper]. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), St. Julian's, Malta. External link
Basile-Bellavance, Y., Lepercq, É., Blaquière, Y., & Savaria, Y. (2008, August). Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL [Paper]. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008). External link
Norman, R., Lepercq, É., Blaquière, Y., Valorge, O., Basile-Bellavance, Y., Prytula, R., & Savaria, Y. (2008, June). An interconnection network for a novel reconfigurable circuit board [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008). External link
Bougataya, M., Lakhsasi, A., Norman, R., Prytula, R., Blaquière, Y., & Savaria, Y. (2008, May). Steady state thermal analysis of a reconfigurable wafer-scale circuit board [Paper]. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008), Niagara Falls, Ont.. External link
Blaquière, Y., Savaria, Y., & El Fouladi, J. (2007, December). Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os [Paper]. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco (4 pages). External link
Poiré, P., Cantin, M.-A., Daniel, H., Blaquière, Y., Savaria, Y., Pocek, K. L., & Arnold, J. M. (1998, April). A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing [Paper]. IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA. External link
Poiré, P., Savaria, Y., Daniel, H., Cantin, M.-A., & Blaquière, Y. (1998, November). Hardware/software codesign of a Fuzzy ART neural clusterer : The benefits of configurable computing [Paper]. 3rd Conference on Configurable Computing, Boston MA, USA. External link
Cantin, M.-A., Blaquière, Y., Savaria, Y., Granger, É., & Lavoie, P. (1998, May). Implementation fo the Fuzzy ART neural network for fast clustering of radar pulses [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 1998), Monterey, CA, USA. External link
Granger, É., Savaria, Y., Blaquière, Y., Cantin, M.-A., & Lavoie, P. (1997). A VLSI architecture for fast clustering with fuzzy ART neural networks. Journal of Microelectronic Systems Integration, 5(1), 3-18. Unavailable
Blaquière, Y., Dagenais, M., & Savaria, Y. (1996). Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), 244-255. External link
Granger, É., Blaquière, Y., Savaria, Y., Cantin, M.-A., & Lavoie, P. (1996, August). VLSI architecture for fast clustering with fuzzy ART neural networks [Paper]. 1st International Workshop on Neural Networks for Identification, Control, Robotics, and Signal/Image Processing (NICROSP 1996), Venice, Italy. External link
Blaquière, Y., & Savaria, Y. (1987). Area Overhead Analysis of SEF: A Design Methodology for Tolerating SEU. IEEE Transactions on Nuclear Science, 34(6), 1481-1486. External link
